Test Engineer

About the role

Test Engineer

Efficient Computer is seeking a Test Engineer to own the end to end test flow for our energy efficient processors. You will define the strategy, build the patterns, and coordinate with foundry and OSAT partners to ensure test programs are executed correctly and production silicon is released on schedule. The role sits at the intersection of hardware engineering and supply chain and operations, requiring equal comfort with technical execution and external collaboration.

The position is based in San Jose, California. It reports to the Hardware Engineering and Supply Chain and Operations organization. The compensation for this role is one hundred forty thousand dollars in base pay and one hundred seventy thousand dollars in total cash.

Test Strategy and Pattern Development

You will translate architectural intent into executable test programs that validate functionality and yield under real operating conditions. This includes owning the intake of DFT requirements and converting block level specifications into executable verification assets. You will generate, validate, and deliver pattern sets for scan, MBIST, JTAG, and embedded memory read and write coverage. In addition, you will develop and maintain STIL and PDL test program files that drive ATE execution. You will own DFT sign off deliverables and resolve pattern level issues in coordination with external design partners. You will define power up and power down sequences, DFT entry sequences, and test mode initialization flows. You will also define power rail sequencing requirements to ensure safe device bringup during test.

ATE Bringup and Test Program Development

You will develop and debug test programs on industry standard ATE platforms from Advantest and Teradyne. You will execute first silicon bringup on new tapeouts in partnership with hardware engineers and OSAT test teams. You will characterize device behavior across voltage, temperature, and frequency corners to confirm correct operation before tapeout. You will support load board bringup and validate interface hardware to ensure test systems are correctly connected. You will define and manage test flows including wafer probe, final test, and bin sort. You will explore test time optimization strategies such as pattern flow sequencing to reduce unnecessary power cycles.

OSAT and Supplier Coordination

You will serve as the primary test engineering interface with OSAT partners and test houses. You will manage test program handoff to OSAT, including documentation, qualification, and acceptance criteria. You will coordinate pattern delivery between design partners and OSAT to ensure format compatibility across STIL and SVF. You will track and analyze yield data from probe and final test, escalate anomalies, and drive corrective actions across multiple chip programs. You will support die traceability and OTP programming flows in production bin sort. You will partner with supply chain and operations on test capacity planning and lot scheduling to keep production on track.

Cross Program Ownership

You will own test engineering for multiple active chip programs at the same time. You will build scalable test infrastructure and documentation that future programs can reuse without rework. You will contribute to DFT reviews, tapeout checklists, and test escape analysis. You will help define and mature internal test engineering capabilities over time.

What You Bring

You have handled the full test lifecycle, including DFT strategy, ATPG pattern generation, ATE bringup, and production test coordination. You can create and validate ATPG patterns for scan, MBIST, JTAG, and embedded memory read and write sequences. You develop and maintain STIL and PDL test program files for ATE execution and drive DFT sign off deliverables. You understand power rail sequencing requirements for safe device bringup during testing. You partner with external design partners and internal hardware engineers while coordinating with OSAT suppliers.

Nice to Have

Experience coordinating with OSAT test houses and managing test program handoff documentation.

Skills and Tools

STIL, PDL, ATPG, ATE, Advantest, Teradyne, SVF, DFT, yield analysis, die traceability, OTP programming.