Lead RTL Design Engineer

About the role

You will own the end-to-end definition and delivery of the RTL implementation for a groundbreaking energy-efficient processor at Efficient Computer. This role centers on architecting and realizing the dataflow execution fabric, memory subsystem, and on-chip interconnect while ensuring strict adherence to power and performance targets. You will translate high-level architecture specifications into synthesis-ready RTL that directly influences the efficiency and capabilities of our compute platform. Collaboration will be integral as you work alongside architects, microarchitects, and firmware teams to align hardware behavior with software expectations. Your contributions will define the low-power intelligence that enables AI/ML to run perpetually on minimal power sources. You will play a key role in establishing the hardware foundation for scalable, pervasive edge intelligence. This position offers the chance to shape foundational technology from initial specification to production tapeout.

Key facts

What you'll do

Architect and define the microarchitecture for the processor core, compute units, dataflow pipelines, and execution engines to meet aggressive performance and efficiency goals.

Drive the specification, design, and integration of on-chip interconnects and network-on-chip fabrics, optimizing for scalability, latency, and bandwidth within physical constraints.

Define the interface and behavior of the memory subsystem, including data movement, ordering semantics, and synchronization primitives to support scalable software models.

Lead the architecture and implementation of reconfiguration mechanisms and the execution model for managing workloads, kernels, and multi-kernel scheduling on the fabric.

Drive power management strategy and low-power design implementation, including clocking, reset, power gating, and retention strategies to achieve target energy efficiency.

Collaborate with compiler and software teams during HW/SW co-design to ensure the hardware execution model enables efficient compilation and workload mapping.

Author and maintain architecture specification documents for assigned blocks, ensuring clarity, correctness, and traceability from spec through implementation.

Mentor senior and junior RTL engineers, providing design reviews, feedback, and guidance to uphold coding standards and mitigate microarchitecture risks.

Participate in physical design analysis loops, synthesizing blocks regularly and evaluating area, timing, and power reports to inform data-driven tradeoffs.

Collaborate with verification and physical design leads to review verification plans and provide directed test scenarios for complex execution flows and power state transitions.

Support silicon bring-up activities, including contributing to scan and ATPG guidelines, reviewing DFT insertion, and aiding RTL-level debug in the lab.

Champion best practices in lint-clean and synthesis-clean RTL coding styles across the design team to ensure robust and maintainable hardware.

Engage with stakeholders to align microarchitecture decisions with system requirements, fabrication processes, and product timelines.

Contribute to the continuous improvement of development processes and documentation to accelerate tapeout and production readiness.

Requirements

8+ years of professional RTL design experience with demonstrated ownership of dataflow-based designs, on-chip networks, memory subsystems, or peripheral integration within processor or accelerator SoCs.

Deep proficiency in SystemVerilog required for synthesis-clean and lint-clean RTL implementation, including complex state machines, arbiters, token flow controllers, and high-performance datapath logic.

Understanding of computer architecture fundamentals, including instruction set interfaces, memory consistency models, cache coherence protocols, and bus-based interconnects.

Experience with low-power design techniques such as clock gating, power gating, retention scanning, and multi-voltage domain strategies essential to meeting energy efficiency targets.

Familiarity with Verilog or VHDL for legacy modules or testbench integration within a broader verification environment.

Strong command of synthesis tools, timing analysis, and physical implementation constraints to enable effective collaboration with place-and-route teams.

Proven ability to work collaboratively in a cross-functional environment with architects, verification engineers, physical designers, compiler developers, and firmware teams.

Excellent written and verbal communication skills necessary for authoring detailed architecture documents and articulating design tradeoffs to technical and non-technical audiences.

Nice to have

Experience with RISC-V ISA and associated peripheral integration such as NVM, I2S, and I2C is preferred.

Background in AI/ML workloads, inference engines, or dataflow accelerators is a strong advantage for this role.

Practical notes

This is a full-time position based in Austin, TX, Pittsburgh, PA, or San Jose, CA.

Relocation assistance is available for qualified candidates.

Candidates must be eligible to work in the United States without sponsorship for this role at this time.

The position requires collaboration across distributed teams and may involve occasional travel to office locations as needed for design reviews or tapeout activities.

Application review will begin immediately and continue until the position is filled.