Lead STA Engineer

About the role

Efficient Computer is seeking a Lead Static Timing Analysis (STA) Engineer to join a newly formed hardware team. This position is central to delivering the world's most energy-efficient general-purpose processor. The role owns the timing methodology and sign-off readiness from early development through to scaled volume production. You will directly influence product behavior at the edge and help define the future of computing. The position is based in San Jose, CA, Pittsburgh, PA, or Austin, TX. It is a full-time role with a competitive compensation package including a salary range of $200,000 to $250,000, equity, and comprehensive benefits.

What you'll do

• Execute the timing sign-off methodology for current finFET process flows using industry-standard tools such as Cadence Tempus or Synopsys Primetime.
• Build and maintain robust analysis flows that ensure timing convergence across all hierarchical levels, including IP, subsystems, and full SoC blocks under aggressive tape-out schedules.
• Champion the definition and enforcement of timing margining, PVTRC corner strategies, and extraction methodologies to guarantee design robustness.
• Ensure strong correlation between synthesized and post-layout timing (SYN/PNR) through rigorous analysis and validation.
• Create custom slew and glitch noise checks to identify and mitigate potential timing violations before tape-out.
• Develop custom static timing checks specific to the company's proprietary ultra-low power architecture to address unique power-state transitions.
• Collaborate with RTL design, DFT, and IP vendor teams to define, implement, and enforce Standard Delay Format (SDC) constraints with precision.
• Partner with post-signal integrity bring-up teams to align pre-si and post-si timing and power objectives for seamless integration.
• Coordinate with third-party vendor resources within strict timing and quality windows to meet project milestones and deliverables.
• Continuously refine flow consistency and efficiency to support multiple product lines and shifting organizational priorities.
• Analyze timing failures and drive closure activities across multi-million gate designs using advanced debugging techniques.
• Mentor junior engineers on timing analysis best practices, tool usage, and methodology documentation.
• Interface with architecture teams to provide early timing feedback during design exploration and optimization phases.
• Establish automated regression suites that provide rapid feedback on timing health across configuration variants.
• Maintain and evolve timing constraints libraries to reflect process, voltage, and temperature variations across the product portfolio.

Requirements

• Hold a Master's degree in Electrical Engineering with over five years of industry experience or a PhD with over three years of experience in a relevant field.
• Demonstrate a proven track record of delivering IP or SoC static timing sign-off through a history of multiple tape-outs in 12nm or below process technologies.
• Possess hands-on expertise with STA and simulation tools from Cadence, Synopsys, or Mentor Graphics as part of standard industry workflows.
• Show extensive experience in timing convergence for high-frequency and low-power designs across complex multi-voltage domains.
• Exhibit deep knowledge of static timing analysis principles including constraint definition, exception handling, corner and voltage binning, and timing margining strategies.
• Demonstrate proficiency in scripting languages such as TCL, shell, and Python to automate analysis, reporting, and data extraction at scale.
• Display strong problem-solving skills with the ability to debug intricate timing issues in large hierarchical designs.
• Communicate effectively with cross-functional engineering teams to align timing objectives with product goals and schedules.
• Adhere to strict quality standards and documentation practices required for production-level tape-outs.
• Understand the impact of process, voltage, and temperature (PVT) variations on timing closure and reliability.
• Experience with low-power techniques such as power gating, clock gating, and retention strategies is essential.
• Familiarity with advanced node constraints and physical-aware timing analysis is required for accurate implementation.
• Commitment to continuous learning and adaptation to new EDA tools, methodologies, and industry standards.

Nice to have

• Knowledge of computer architecture is beneficial for understanding the impact of design choices on timing behavior.
• Experience with full chip sign-off budgeting to manage timing, power, and area trade-offs effectively.
• Exposure to integrating analog or mixed-signal macros within a primarily digital timing flow.
• Background in building physical design CAD flow infrastructure to support efficient timing analysis.
• Familiarity with circuit design, device physics, deep sub-micron technology, and SOI technology and its impact on physical design.
• Understanding of how SOI technology influences leakage, speed, and overall timing closure strategies.

Practical notes

• The listing for the specifies locations in San Jose, CA, Pittsburgh, PA, or Austin, TX.
• The engagement type and detailed hours are available
• Compensation details, including the specific salary within the $200,000 to $250,000 range, equity grants, and benefits, are confirmed
• Candidates must refer to the official apply page to confirm the current requirements and eligibility criteria for the Lead STA Engineer role.
• This role requires the ability to work on-site or as specified in the location options provided.
• Travel requirements, if any, and visa sponsorship details should be verified directly with the information provided
• Applicants are encouraged to submit their materials through the official channel to ensure full consideration for the position.
• The start date and schedule are determined by the hiring team and published
• All application instructions, including document submissions and contact information, are outlined