Lead Digital Verification Engineer

About the role

You will define and execute the end-to-end verification strategy for complex SoC and IP designs from specification through tapeout within a newly formed hardware engineering organization. You own the verification methodology, quality standards, and sign-off readiness, acting as the final authority on verification completeness and correctness. This role requires deep expertise in modern verification techniques such as UVM, embedded C, and compiler-generated trace-driven testing, combined with strong leadership to guide and grow a multi-block chip verification team. You will shape internal verification processes and contribute to both the current product line and the company's second product that scales computing performance while enhancing energy efficiency. The position gives you influence over products and processes as the organization moves from early development into market release and scaled production. You will play a key role in defining verification infrastructure, driving quality, and enabling the deployment of pervasive, energy-efficient intelligence at the edge.

Key facts

What you'll do

Define the end-to-end verification strategy across block, subsystem, and full-chip levels aligned with tapeout milestones.

Author and review verification plans mapping specifications to features, stimulus strategies including traditional stimulus generation and compiler driven approaches, coverage goals, and sign-off criteria.

Architect scalable UVM-based testbench environments including agents, scoreboards, reference models, and coverage monitors.

Drive constrained-random stimulus development targeting protocol interactions, concurrency, error injection, and corner cases.

Define and close functional coverage models through systematic hole analysis, targeted tests, seed optimization, and regression tuning.

Deploy SystemVerilog Assertions for protocol compliance, interface checks, and design invariants across all simulation runs.

Lead full-chip verification including boot sequences, interrupt handling, DMA flows, power-on reset, and multi-block interactions.

Ensure CDC, RDC, and multi-power-domain verification in coordination with specialist tools and teams.

Debug complex simulation failures spanning multi-block interactions, protocol violations, race conditions, and timing-dependent corner cases.

Own the bug lifecycle - triage, prioritization, tracking, fix verification, and cross-functional resolution with RTL designers and architects.

Manage the regression framework - defining suites, maintaining stability, optimizing throughput, and integrating with CI/CD pipelines.

Coordinate simulation-to-emulation handoff ensuring verification collateral transitions effectively to emulation environments.

Collaborate cross-functionally with Compiler Team, RTL design, DFT, physical design, and post-silicon validation teams.

Lead, mentor, and grow the verification engineering team while maintaining a high quality bar through rigorous reviews.

Represent verification readiness in tapeout sign-off reviews and program-level decisions.

Support running gate-level simulations as part of design signoff.

Assist in building a verification dashboard to quickly understand where a design is in the verification process and to identify regressions.

Requirements

8+ years of proven experience in digital design verification for ASIC or SoC projects using UVM.

Strong proficiency in SystemVerilog, testbench architecture, and constrained-random verification methodologies.

Demonstrated experience with compiler generated trace, embedded C, and simulation-based verification flows.

Solid understanding of protocol standards such as AXI, AHB, APB, and common interface protocols relevant to SoC designs.

Experience with full-chip verification, boot sequences, power-on reset, interrupt handling, and DMA flow verification.

Expertise in CDC, RDC, and multi-power-domain verification techniques and associated tool flows.

Track record of defining and closing functional coverage models, including hole analysis and coverage-driven test planning.

Strong debugging skills for simulation failures involving multi-block interactions, race conditions, and timing-dependent corner cases.

Ability to lead and mentor verification engineers, conduct design reviews, and enforce verification quality standards.

Excellent written and verbal communication skills to collaborate effectively with cross-functional teams and represent verification in tapeout reviews.

Nice to have

Experience with second-generation energy-efficient computing platforms and emerging AI/ML workloads at the edge.

Familiarity with automated regression optimization, continuous integration, and hardware CI/CD pipelines.

Understanding of compiler-driven test generation and trace-based verification flows.

Exposure to simulation-to-emulation handoff and hybrid verification environments.

Practical notes

Location options include San Jose, CA; Pittsburgh, PA; and Austin, TX.

Engagement details are to be confirmed from source information.

No compensation details are provided in the source material.

The role involves collaboration across verification, design, compiler, and post-silicon teams with an emphasis on quality and timely tapeout.

Applicants should be prepared to participate in debugging complex issues across block and full-chip domains.

The position supports the development of next-generation hardware that enables pervasive, energy-efficient intelligence at the edge.