Physical Design - SOC Top Lead

About the role

Lead Physical Design Engineer, SOC Top

Efficient is developing the world's most energy-efficient general-purpose computer processor. The company's patented technology achieves 100 times the energy efficiency of current ultra-low-power processors. The platform is programmable using standard high-level languages and AI/ML frameworks. This efficiency enables perpetual, pervasive intelligence, allowing AI/ML to run continuously on an AA battery for five to ten years. The technology enables IoT devices to capture and curate first-party data, driving the next major computing revolution.

Efficient is seeking a Lead Physical Design Engineer to assume end-to-end ownership of the System-on-Chip (SoC) top deck for next-generation processors. This is a high-accountability, hands-on role. You will be the single point of ownership guiding the chip from initial block integration through timing, power, signal integrity, and physical closure to tapeout-ready GDS. You will collaborate with block-level physical design owners, DFT teams, package and IO groups, and the architecture team. This position is within the newly formed hardware engineering group and focuses on designing using state-of-the-art finFET technologies. This is an opportunity to influence products from early development to market release and scaled production.

Key Responsibilities

You will establish and enforce the floorplanning strategy for chip-level integration, ensuring clean block integration under strict timelines. You will own power planning and PDN design, performing analysis for IR drop and electromigration to prevent issues before first silicon. You will drive full-chip timing closure across all operational modes and corners, managing OCV and cross-boundary timing while owning the chip-level constraint methodology. You will oversee physical verification, achieving DRC, LVS, and antenna closure at the top level and managing seal ring integration. You will address signal integrity and noise challenges, focusing on crosstalk and di/dt mitigation around high-speed IO and PLL/analog boundaries. You will architect the top-level clock and reset strategy, coordinating clock tree synthesis with block owners. You will lead chip-level DFT integration, including scan stitching, MBIST, and JTAG, working with the DFT lead on ATPG and coverage targets. You will coordinate package and IO co-design, including bump and ball map planning and package-aware floorplanning. You will own the tapeout readiness sign-off checklist, ensuring timing, power, physical, and reliability criteria are met for final GDS handoff. You will serve as the primary liaison between block-level PD owners, DV, DFT, package engineering, and architecture, resolving convergence risks and schedule issues. You will provide technical leadership, mentoring block-level physical design engineers and establishing methodology and flow standards for chip-level closure.

Required Qualifications

You hold a Master's degree in Electrical Engineering with five or more years of industry experience or a PhD in Electrical Engineering with three or more years of industry experience. You bring eight to twelve or more years of physical design experience, including two to three full tapeouts at the chip-top or SoC integration level, not solely block-level work. You possess deep hands-on experience with advanced finFET nodes and their specific constraints. You have a proven record of owning full-chip timing closure across multiple modes and corners for complex SoCs. You have strong PDN, IR-drop, and electromigration analysis experience using tools such as Voltus or equivalent platforms. You have led chip-level DFT integration, including scan stitching and ATPG coverage. You are familiar with flip-chip, BGA, and bump array arrangements for demanding packages. You use Innovus or ICC2, along with Tempus, PrimeTime, RedHawk, and Calibre, on a daily basis. You can guide engineers toward convergence while aligning schedules across distributed global teams.

Professional Context

This role is based in San Jose, California, or Pittsburgh, Pennsylvania, or Austin, Texas. The engagement is full-time. The compensation range is $180,000 to $260,000 per year.

Nice to Have

Experience mentoring physical design engineers at the chip top level within demanding, high-volume programs.

Tools and Skills

Proficiency with Innovus, Tempus, RedHawk, and Calibre is essential.

Practical Notes

Please You are responsible for your application and all materials submitted.

What you'll do

• Meet the bar