Software Engineer, Kernel Development and Optimization

About the role

Tenstorrent is building custom RISC-V CPU and AI processor architectures to redefine computing performance. This role is focused on optimizing low-level kernels and machine learning workloads to ensure high-efficiency software execution across the compute stack. The successful candidate will own the implementation and tuning of critical software components that bridge hardware capability and application requirements. You will work closely with hardware teams to validate designs and drive performance improvements at the firmware and systems level. The position demands a deep understanding of how algorithms map to silicon and how to extract maximum throughput from complex compute architectures. You will be responsible for ensuring that software tools keep pace with rapidly evolving hardware generations. This role is integral to delivering the performance and efficiency that define Tenstorrent's product vision.

Key facts

What you'll do

• Architect and implement low-level kernel modules, taking ownership of the full development lifecycle from design to deployment.
• Profile and isolate performance regressions within complex software stacks, applying advanced debugging strategies to stabilize runtime environments.
• Engineer data pathways to minimize latency and maximize throughput in tensor compute operations across heterogeneous compute grids.
• Partner with hardware architects to refine instruction set utilization and memory subsystem behavior for optimal silicon efficiency.
• Optimize the flow of data and compute tasks to scale large language models across distributed processing units and compute fabrics.
• Develop high-performance primitives that accelerate machine learning workloads, focusing on numerical efficiency and parallel execution.
• Instrument systems with detailed telemetry, using performance profiling data to guide iterative optimization efforts.
• Translate abstract ML framework requirements into concrete, low-level implementations that leverage RISC-V and related vector processing concepts.
• Collaborate with cross-functional teams to define coding standards and verification methodologies for kernel-level software.
• Mentor junior engineers on best practices for writing robust, high-throughput systems software.

Requirements

• Demonstrate strong proficiency in C and C++, with a portfolio of work showcasing complex system-level programming.
• Provide evidence of writing high-performance, low-level code that targets demanding computational workloads.
• Show practical experience in developing and optimizing data movement kernels and tensor compute operations.
• Exhibit fluency with performance profiling tools and methodologies for diagnosing issues in intricate runtime contexts.
• Prove ability to read and interpret technical specifications to implement features that align with hardware capabilities.
• Display a track record of debugging difficult issues in systems where software interacts directly with hardware.
• Hold eligibility to access U.S. export-controlled technology, which may require U.S. citizenship, permanent residency, or a valid U.S. Commerce Department license.
• Commit to adhering to all U.S. Export Administration Regulations concerning the development and distribution of sensitive technologies.

Nice to have

• Hands-on experience with GPU programming using CUDA or OpenCL to accelerate compute-intensive tasks.
• Solid understanding of operating system internals, including scheduling, memory management, and device driver interactions.

Practical notes

• Candidates of all seniority levels are encouraged to apply. Offers will be adjusted based on assessment during the interview process.
• Employment is contingent upon eligibility to access U.S. export-controlled technology. This may require citizenship, permanent residency, or a license from the U.S. Commerce Department due to U.S. Export Administration Regulations. Offers will be rescinded if export law compliance cannot be met.

The role of is centered on pushing the boundaries of what is possible in AI and high-performance computing. You will be responsible for ensuring that the software stack extracts every ounce of capability from the underlying hardware. A significant portion of your work will involve close collaboration with hardware engineers, allowing you to influence the direction of silicon development based on software requirements. You will need to balance theoretical knowledge with the practical realities of debugging systems where hardware and software intersect. The position requires a meticulous approach to problem-solving and a commitment to writing code that is both fast and reliable.

This position is located in either Gdańsk, Pomeranian Voivodeship, Poland or Warszawa, Masovian Voivodeship, Poland. The engagement model is hybrid, allowing for a combination of remote work and time spent in the office. This setup is designed to foster collaboration during critical design discussions while providing flexibility for deep-focus work. The company culture values autonomy, ownership, and a high degree of technical rigor. You should be comfortable working in an environment that moves quickly and requires adaptability.

Because the role involves access to sensitive technology, candidates must meet specific eligibility requirements related to U.S. export control laws. These regulations are strict and govern who can work on certain types of hardware and software. It is essential that applicants are transparent about their eligibility during the application process. The company cannot sponsor visas for this role if it conflicts with these regulations. Therefore, candidates must possess the necessary rights to access U.S. technology without restriction. This typically includes being a citizen or permanent resident of the United States or another country with equivalent access rights.

The compensation for this role is not specified in the public listing. The engagement type is listed as hybrid, which defines the work arrangement. Candidates should note that offers may be adjusted based on the results of assessments conducted during the interview process. This ensures that the final offer reflects the actual capabilities and contributions of the candidate. The interview process is designed to evaluate both technical proficiency and cultural fit.

Tenstorrent is building a new generation of computing infrastructure. Success in this role requires a proactive attitude and a willingness to tackle ambiguous problems. You will not only write code but also participate in high-level discussions about system architecture. The ability to communicate technical concepts clearly is highly valued. If you are passionate about systems programming and eager to work on cutting-edge hardware, this position represents a significant opportunity.