Staff Engineer, RTL Implementation

About the role

Staff Engineer, RTL Implementation

Tenstorrent is at the forefront of AI hardware innovation, challenging conventional computing models to deliver unprecedented performance, usability, and value. Our mission is fueled by a team of technologists who have engineered a high-performance RISC-V CPU architecture from the ground up. This pursuit demands collaborators who are passionate about AI and dedicated to constructing the most advanced computing platform possible. We operate with a spirit of collaboration, relentless curiosity, and a commitment to overcoming complex challenges. As we expand our capabilities, we seek engineers of all levels to join this mission.

This position is a hybrid role, with work split between our Austin, Texas and Santa Clara, California offices.

The Role

You will own a critical lane within the CPU implementation flow, guiding the RISC-V design from initial register transfer level (RTL) verification through to final tapeout. Your primary responsibility is to balance timing, power, and area (PPA) while ensuring physical design integrity. You will work in close partnership with CPU architects and verification groups to stabilize micro-architecture choices and keep project schedules on track. Your decisions in the register-transfer level (RTL) and physical flow directly shape the final hardware behavior.

Staff Engineer, RTL Implementation

• Setting physical design strategy for new engine IP while aligning with product goals and target process technologies.
• Guiding synthesis and place and route execution for current CPU cores and legacy IP to achieve stable, high-quality tapeouts.
• Planning and running power, performance, and area experiments, then analyzing the results to define actionable optimization strategies.
• Leading deep collaboration with micro-architects, design verification (DV), physical design (PD), and RTL teams to achieve unified timing and power convergence.
• Championing improvements to the physical design environment, toolchains, and methodologies to boost team efficiency and output quality.
• Driving the evaluation of novel optimization techniques, verifying that PPA targets are successfully met.
• Partnering with external groups to reconcile design intent and resolve functional or physical issues before final signoff.
• Maintaining end-to-end awareness of the design from initial concept through timing and power convergence at every tapeout.

Requirements

• Demonstrated high-performance physical design experience, including mastery of synthesis and place and route flows.
• Expert-level proficiency in Verilog or VHDL, with daily experience using simulation and power analysis tools.
• Deep understanding of CPU micro-architecture and the ability to collaborate on core configuration and optimization decisions.
• The ability to work in the United States and comply with U.S. export control regulations regarding controlled technology.

Nice to Have

• A record of improving physical design environments, toolchains, and methodologies to elevate development efficiency.

Compensation and Benefits

Compensation for this role ranges from $100,000 to $500,000. Total rewards include base salary and variable compensation targets. Factors such as an individual's experience, technical skills, educational background, and work location influence the final offer. Tenstorrent provides a highly competitive benefits package and is an equal opportunity employer.

What You Will Learn

• Complete exposure to the CPU design flow, from high-level architecture down to timing and power convergence.
• Hands-on experience optimizing CPU designs to drive meaningful PPA improvements.
• Practical experience integrating open-source and industry-standard tools to enhance physical design flows and outcomes.
• The opportunity to solve current CPU design challenges within a deeply technical and highly collaborative team environment.

Practical Information

Please confirm specific details on the official application page.

Equal Opportunity Statement

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including the U.S. Export Administration Regulations (EAR), the company is required to ensure compliance when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.