Physical Design Engineer, AI Accelerator IP

About the role

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. You will own the physical implementation of AI accelerator IP blocks end to end, translating architectural intent into signoff-quality GDSII through synthesis, floorplanning, power grid design, placement, clock synthesis, routing, and final signoff. You will directly influence how quickly we can commit to customer timelines by delivering robust, PPA-verified deliverables. You will collaborate tightly with architecture and RTL teams to resolve design issues and ensure that hardened IP meets the strictest reliability and performance standards. Your work will be integrated into multi-die chiplet solutions and licensed to customers who rely on this IP to ship their own products.

Key facts

What you'll do

Investigate and resolve physical design issues across multiple abstraction levels to accelerate IP tapeout decisions.

Collaborate with architecture and RTL owners to define block-level strategies that balance performance, power, and area targets.

Lead block-level implementation flows using industry-standard tools to ensure timing, power, and signoff compliance.

Drive floorplanning and power grid design for IP blocks to support low-power modes, multi-Vt selection, and voltage scaling scenarios.

Execute pin placement and clock tree synthesis to meet strict latency, skew, and routing congestion objectives.

Generate and validate timing and power models for IP integration collateral, including LEF, DEF, and standard cell libraries.

Perform signoff analysis including static timing analysis, power analysis, and layout versus schematic verification.

Partner with cross-functional teams to port the same IP across nodes, foundries, and PPA targets while maintaining delivery schedules.

Own integration deliverables such as GDSII, timing reports, and power data for customer consumption and tapeout signoff.

Support advanced node challenges related to process variation, density, and electromigration to ensure robust IP in volume manufacture.

Implement structured and custom design techniques that optimize routability, congestion, and signal integrity for AI accelerator structures.

Document methodologies, results, and decisions to enable consistent execution and knowledge transfer across design teams.

Champion best practices in physical design to improve reusability, quality, and predictability of IP delivery.

Engage in hands-on debugging of timing violations, power hotspots, and DRC violations to meet risk-free release criteria.

Contribute to continuous improvement of physical design flows and tool methodologies in a fast-paced RISC-V environment.

Requirements

BS/MS/PhD in EE/ECE/CE/CS with 5+ years of block-level or IP-centric physical design through tapeout.

Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl).

Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage scaling), and signoff (STA, LEC).

Experience building floorplans, power grids, pin placement, and clocking strategies, and delivering IP integration collateral (LEF/DEF, timing and power models, GDS, signoff reports).

Strong knowledge of placement, clock synthesis, routing, and post-layout signoff flows in advanced technologies.

Demonstrated ability to close critical paths, manage timing exceptions, and respect power budgets in complex designs.

Commitment to rigorous signoff discipline because IP ships to customers who integrate it without you in the room.

Familiarity with RISC-V CPU and AI accelerator design concepts, and how they map to physical implementation constraints.

Practical notes

This role is hybrid, based out of Toronto, ON; Austin, TX; or Belgrade, Serbia.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.