Staff, RTL Engineer

About the role

Tenstorrent is building high-performance RISC-V CPUs and AI accelerators from the ground up. We are looking for engineers to lead microarchitecture and RTL development for our next generation of silicon products. In this capacity, you will own the specification and delivery of critical digital blocks that directly impact silicon functionality and performance. You will act as a primary driver for microarchitecture decisions that balance aggressive power targets with demanding throughput requirements. The role requires you to own complex digital subsystems end-to-end, ensuring that architectural intent is precisely realized in gate-level implementations. You will be responsible for ensuring that our designs meet strict quality and reliability standards before tapeout. This position is integral to the successful execution of our silicon roadmap and product differentiation in the market.

Key facts

What you'll do

• Design and implement RTL for digital subsystems, fabrics, and SoC-level integrations, ensuring correctness and robustness.
• Manage microarchitecture development while balancing power, performance, and area requirements to meet product specifications.
• Collaborate with architecture, verification, physical design, and DFx teams to align implementation with system-level objectives.
• Perform pre-silicon and post-silicon debugging, including silicon bring-up and root-cause analysis to resolve complex issues.
• Contribute to the full silicon lifecycle from initial concept to final production, guiding decisions from specification to deployment.
• Develop and maintain verification environments and testbenches to validate RTL functionality against architectural protocols.
• Optimize register transfer level code for timing, area, and power efficiency across diverse operational scenarios.
• Define and implement interfaces to external cores and IP, ensuring compliance with standards such as AXI, AHB, APB, I3C, and SPI.
• Support the integration of RISC-V CPU cores and associated logic, focusing on coherence and protocol correctness.
• Document design decisions, verification strategies, and debugging procedures to support long-term maintenance and reuse.

Requirements

• Hold a Bachelor, Master, or PhD in Electrical Engineering, Computer Engineering, or Computer Science from an accredited institution.
• Possess a minimum of 5 years of professional experience in ASIC, SoC, or chiplet development within the semiconductor industry.
• Demonstrate proficiency in Verilog-based design and fluency with industry-standard simulation and synthesis tools used in tapeout projects.
• Show expertise in digital subsystem integration and protocols including AXI, AHB, APB, I3C, and SPI, with a deep understanding of their behaviors.
• Exhibit strong ability to solve complex logic and system-level design challenges under tight schedule and quality constraints.
• Have a track record of delivering production-quality RTL that meets timing, power, and functional coverage goals.
• Be capable of working independently and as part of a cross-functional team in a fast-paced, deadline-driven environment.
• Understand the implications of U.S. export control regulations as they apply to semiconductor design and technology transfer.

Nice to have

• Experience with RISC-V CPU cores, including hands-on integration and optimization for AI and high-performance workloads.
• Familiarity with DFT/DFD methodologies such as scan test, MBIST, JTAG, and ATPG to enable efficient manufacturing test and debug.
• Background in open-source hardware projects, contributing to or maintaining community-driven designs and interfaces.
• Knowledge of chip-level debug architectures, including tracing, instrumentation, and analysis of system behavior.

Practical notes

Compensation ranges from $100k to $500k, including base salary and variable components, determined by experience, education, and location. Employment is contingent upon the candidate being eligible to access U.S. export-controlled technology. Offers may require citizenship, permanent residency, or a license from the U.S. Commerce Department due to export control regulations. Candidates will be assessed for the appropriate seniority level during the interview process. This position is remote, but candidates must be located in the United States or New Taipei City, Taiwan, to comply with operational and regulatory requirements. No business travel is required for this role. There are no specific visa sponsorship details provided at this time; interested candidates should refer to official company policies for immigration support if applicable. The posting is active until the position is filled, and early application is encouraged to ensure full consideration.