RISC-V AI / HPC & Agentic Software Engineering Lead

About the role

Tenstorrent is developing specialized RISC-V CPUs designed for high-performance computing and autonomous AI systems. This leadership position focuses on the intersection of hardware and software, where you will build the infrastructure required to run agentic AI and HPC workloads on our proprietary silicon. You will own the end-to-end software stack that bridges the silicon capabilities to the AI workloads, ensuring that the hardware is fully utilized and the software delivers on the performance promises. Your work will directly influence how developers interact with next-generation compute infrastructure and how efficiently complex agentic behaviors are executed on the RISC-V ecosystem. You will be responsible for establishing the software foundation that allows our hardware to excel in demanding computational environments. This role requires a deep understanding of how low-level system design impacts high-level application performance and reliability. You will act as a technical leader guiding cross-functional teams to deliver robust and scalable software solutions.

Key facts

What you'll do

• Integrate and refine the Low-Level Kernel (LLK) infrastructure to support efficient CPU execution and stability.
• Lead the conception and implementation of a RISC-V native software stack specifically tailored for agentic AI, including runtime orchestration and distributed execution frameworks.
• Architect and optimize memory systems to align with the demands of goal-oriented AI applications and high-throughput computing scenarios.
• Design and maintain developer tools that abstract hardware complexity and enable rapid prototyping for specialized AI workloads.
• Partner closely with CPU architects to ensure that microarchitectural features are exposed effectively to the software layer.
• Collaborate with compiler engineers to maximize instruction-level parallelism and leverage custom ISA extensions for performance gains.
• Drive the optimization of performance-critical code paths to meet the stringent latency and throughput requirements of HPC workloads.
• Evaluate and integrate distributed execution frameworks to enable scalable deployment across heterogeneous compute resources.
• Implement vectorization strategies and custom ISA extensions to accelerate specific AI and HPC kernels.
• Establish best practices for accelerator integration, ensuring seamless communication between software components and hardware units.

Requirements

• Bring a background in HPC and AI software development with a proven track record of delivering high-performance systems.
• Demonstrate deep knowledge of RISC-V architecture, including its Instruction Set Architecture, available extensions, and micro-architectural implications.
• Show proficiency in systems-level programming using C and C++ to write efficient and maintainable codebases.
• Have hands-on experience with agentic AI frameworks, distributed execution models, or complex orchestration platforms.
• Exhibit the ability to analyze and optimize performance-critical sections of code under real-world constraints.
• Possess familiarity with modern compiler toolchains, specifically LLVM or GCC, to enable advanced code generation and optimization.
• Highlight experience with vectorization techniques, custom ISA modifications, or integration with specialized accelerators.
• Understand the constraints and capabilities of running large-scale distributed workloads in a remote and potentially regulated environment.

Skills & tools

• C/C++
• RISC-V ISA
• LLVM/GCC
• Distributed execution frameworks
• Low-level kernel optimization

Practical notes

Compensation ranges from $100,000 to $500,000, including base and variable pay, determined by your skills, experience, and location. Employment is contingent upon your eligibility to access U.S. export-controlled technology. You must be able to comply with U.S. Export Administration Regulations, which may require citizenship or permanent residency status, or the ability to obtain a license from the U.S. Commerce Department. Candidates will be assessed for the appropriate seniority level during the interview process.