Sr. Engineer, CPU RTL Design
Job description
About the role
About the role Join the CPU design team at Tenstorrent to define and build RTL for high-performance processors based on the RISC-V ISA. You will partner with design verification, physical design, and performance teams to deliver designs that meet functional, timing, and power targets. Candidates at different experience levels are welcome and will be evaluated during interviews for the appropriate seniority. Key facts
Location: USA
Engagement: Full-time
Team: CPU Design What you'll do
Take ownership of RTL design and microarchitecture development for a specific block within a high-performance RISC-V CPU
Work alongside DV, PD, and performance engineers to hit functional correctness, timing closure, and power objectives
Apply creative approaches to optimize power, performance, and area while running RTL experiments and analyzing outcomes
Collaborate with validation and test groups to support both pre-silicon and post-silicon execution
Improve the RTL design environment, tooling, and workflows to increase team productivity Requirements
Hands-on CPU microarchitecture experience in areas such as Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache, or Datapath
Proficiency in RTL coding using Verilog or VHDL
Familiarity with standard EDA tools for simulation, synthesis, and power analysis
Ability to debug RTL and logic issues across multiple design hierarchies in pre-silicon and post-silicon settings
Background in microarchitecture definition, design specification, and performance trade-off analysis Skills & tools
Verilog, VHDL
Simulation, synthesis, and power analysis tools
Pre-silicon and post-silicon debug methodologies
RISC-V ISA Practical notes
Total compensation ranges from $100k to $500k, including base salary and variable targets; actual offers depend on experience, skills, education, background, and location
Employment is contingent on eligibility to access U.S. The listing location is Austin, Texas, United States; Santa Clara, California, United States.
Key facts
What you'll do
- Take ownership of RTL design and microarchitecture development for a specific block within a high-performance RISC-V CPU
- Work alongside DV, PD, and performance engineers to hit functional correctness, timing closure, and power objectives
- Apply creative approaches to optimize power, performance, and area while running RTL experiments and analyzing outcomes
- Collaborate with validation and test groups to support both pre-silicon and post-silicon execution
- Improve the RTL design environment, tooling, and workflows to increase team productivity
- Hands-on CPU microarchitecture experience in areas such as Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache, or Datapath
- Proficiency in RTL coding using Verilog or VHDL
- Familiarity with standard EDA tools for simulation, synthesis, and power analysis
- Ability to debug RTL and logic issues across multiple design hierarchies in pre-silicon and post-silicon settings
- Background in microarchitecture definition, design specification, and performance trade-off analysis
- Simulation, synthesis, and power analysis tools
- Pre-silicon and post-silicon debug methodologies
Requirements
- Candidates at different experience levels are welcome and will be evaluated during interviews for the appropriate seniority.
- Key facts
Location: Austin, TX or Santa Clara, CA (hybrid)
Engagement: Full-time
Team: CPU Design What you'll do
Take ownership of RTL design and microarchitecture development for a specific block within a high-performance RISC-V CPU
Work alongside DV, PD, and performance engineers to hit functional correctness, timing closure, and power objectives
Apply creative approaches to optimize power, performance, and area while running RTL experiments and analyzing outcomes
Collaborate with validation and test groups to support both pre-silicon and post-silicon execution
Improve the RTL design environment, tooling, and workflows to increase team productivity Requirements
Hands-on CPU microarchitecture experience in areas such as Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache, or Datapath
Proficiency in RTL coding using Verilog or VHDL
Familiarity with standard EDA tools for simulation, synthesis, and power analysis
Ability to debug RTL and logic issues across multiple design hierarchies in pre-silicon and post-silicon settings
Background in microarchitecture definition, design specification, and performance trade-off analysis Skills & tools
Verilog, VHDL
Simulation, synthesis, and power analysis tools
Pre-silicon and post-silicon debug methodologies
RISC-V ISA Practical notes
Total compensation ranges from $100k to $500k, including base salary and variable targets; actual offers depend on experience, skills, education, background, and location
Employment is contingent on eligibility to access U.S.
- export laws, including the Export Administration Regulations (EAR); candidates from EAR Country Groups D:1, E:1, and E:2 may require prior license approval from the U.S.
About Tenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors.
Design roles shape how people understand a product. Research, flows, and visual systems sit together so the interface stays coherent as features grow. Critique and handoff to engineering are part of the week. Tasks stay those the employer listed. These sentences describe the discipline, not extra screens to invent.
About the location
The posting places this role in Austin, Texas, United States; Santa Clara, California, United States. Local hiring markets vary in interview pace and compensation bands. Location copy is here so readers understand the geography attached to the title.