CPU Architect, Load-Store

About the role

Tenstorrent is actively engaged in the design and implementation of high-performance RISC-V CPUs to form the foundational compute engine of its AI platform. This specific role is situated within the dedicated processor architecture team, where you will concentrate exclusively on the load-store unit responsible for data movement and memory coherence. The position is open to candidates spanning a range of experience levels, and the evaluation process during interviews will assess your fit across multiple dimensions, with the final compensation offer tailored to the assessed level of contribution. You will be expected to operate with a high degree of ownership over the entire lifecycle of the load-store unit, from initial architectural conception through to detailed micro-implementation and validation. The role demands a blend of deep technical insight and practical execution, focusing on how data is fetched from and stored to memory in an out-of-order execution environment. Success in this position will directly impact the throughput, latency, and energy efficiency of the overall CPU core. You will be part of a broader effort to build processors from the ground up, ensuring that the memory subsystem is robust enough to support the demanding needs of modern AI workloads.

Key facts

What you'll do

• Architect and define the load-store unit for high-performance out-of-order RISC-V processors, determining its micro-structural components and data flow.
• Engineer novel mechanisms to optimize the load-store unit for power consumption, execution performance, and silicon area efficiency.
• Execute detailed simulations and construct analytical models to evaluate the behavior of advanced CPU features and modern data prefetchers under diverse workloads.
• Liaise closely with hardware and software teams to refine memory access patterns, debug performance bottlenecks, and elevate overall system throughput.
• Monitor and analyze the latest research developments in CPU architecture and memory subsystem design to identify opportunities for innovation.
• Author comprehensive documentation that captures architectural decisions, trade-offs, and empirical results for internal and external consumption.
• Prepare clear and persuasive presentations that articulate the value and implications of architectural choices to both technical and non-technical stakeholders.
• Apply performance profiling tools and benchmarking methodologies to validate hypotheses and guide iterative improvements to the load-store unit.
• Collaborate on the integration of the load-store unit with other core components to ensure coherence and efficient inter-core communication.
• Contribute to the definition of test strategies and verification plans that ensure the reliability and correctness of the architectural implementation.

Requirements

• Hold a Bachelor's or Master's degree in Computer Engineering, Electrical Engineering, Computer Science, or possess equivalent practical experience that demonstrates the same level of competence.
• Exhibit a solid and intuitive grasp of computer architecture fundamentals, including but not limited to memory hierarchy, cache coherence protocols, and data prefetching algorithms.
• Bring demonstrable experience with performance modeling and simulation tools such as Gem5, SimpleScalar, or other comparable quantitative analysis platforms.
• Show working knowledge of hardware description languages like Verilog or VHDL, coupled with the ability to write system-level programming in C or C++.
• Possess the ability to deconstruct and analyze complex system-level interactions, isolating root causes and understanding ripple effects across the design.
• Demonstrate strong written and verbal communication skills, fostering a collaborative mindset that thrives in cross-functional team environments.
• Have hands-on experience with performance profiling tools and formal benchmarking methods to measure and compare architectural performance.
• Show familiarity with parallel processing architectures, multi-core systems, and the challenges associated with scaling across multiple processing elements.

Skills & tools

• RISC-V architecture
• Gem5, SimpleScalar, or similar simulators
• Verilog, VHDL
• C, C++
• Performance profiling and benchmarking utilities

Practical notes

• Total compensation ranges from $100k to $500k, combining base salary and variable targets; actual offers depend on experience, skills, education, background, and location
• Employment is contingent on eligibility to access U.S. export-controlled technology under U.S. export laws including the Export Administration Regulations (EAR); applicants subject to EAR Country Groups D:1, E1, or E2 may require prior license approval from the U.S. Commerce Department or another federal agency
• Equal opportunity employer