Advanced Packaging Lead

About the role

QuantWare is pushing the boundaries of quantum computing by developing high-performance processors built on proprietary VIO technology designed to scale to MegaQubit levels. The company is looking for a technical authority to take ownership of the assembly and integration of complex multi-layer chip stack architectures. In this position, you will spearhead the engineering of packaging processes, ensuring that hardware consistently hits rigorous performance benchmarks. You will act as the primary driver for maturing back-end fabrication techniques from development into reliable, repeatable manufacturing flows. This is a hands-on leadership role situated at the intersection of materials science, microwave engineering, and quantum hardware integration.

Key facts

What you'll do

• Lead the advancement of back-end assembly and fabrication methodologies with a specific emphasis on flip chip bonding techniques, contact reliability optimization, and overall manufacturability readiness.
• Design and govern comprehensive integration test plans while coordinating closely with cross-functional teams spanning design, fabrication, and measurement.
• Establish and formalize assembly-centric fabrication processes alongside development standards to create a unified technical baseline across the organization.
• Architect and document scalable integration workflows that support the company's roadmap toward large-scale quantum processor deployment.
• Diagnose and resolve complex technical anomalies and integration bottlenecks that threaten device performance specifications or yield targets.
• Collaborate with process engineers and physicists to define critical material stacks and interface requirements for superconducting multi-chip modules.
• Drive the selection, qualification, and management of external vendors and foundry partners for critical packaging sub-processes and materials.
• Implement statistical process control and metrology strategies to monitor key packaging parameters such as bump height uniformity, adhesion strength, and RF loss.
• Contribute to the intellectual property portfolio by identifying patentable innovations within the packaging and assembly domain.
• Mentor junior engineers and technicians, fostering a culture of rigorous documentation and first-principles problem solving within the R&D team.

Requirements

• Minimum of four years of professional experience developing chip assembly processes within deep-tech, semiconductor, or low-volume high-complexity manufacturing environments.
• Demonstrated practical expertise in back-end process flows, including Under Bump Metallization (UBM) schemes, hard-stop structures, bump formation, MEMS integration, detachable contact technologies, and flip-chip attachment methods.
• Academic foundation in physics, microwave engineering, RF engineering, electrical engineering, materials science, or a closely related technical discipline.
• Proven ability to work independently in a cleanroom or lab setting, defining process modules and executing experimental splits to optimize yield.
• Strong analytical skills for failure analysis, including proficiency with optical inspection, SEM, X-ray tomography, and electrical characterization of interconnects.
• Excellent written and verbal communication skills in English for technical reporting and cross-team collaboration in an international setting.

Nice to have

• A PhD in a relevant field such as applied physics, electrical engineering, microsystems technology, or materials science.
• Direct hands-on background working with superconducting qubit devices or quantum processor hardware integration.
• Familiarity with cryogenic packaging constraints, including thermal expansion matching, magnetic shielding, and loss tangent minimization at millikelvin temperatures.
• Experience with design tools such as Ansys HFSS, COMSOL, or Cadence for electromagnetic and thermo-mechanical simulation of packaging structures.
• Prior involvement in scaling processes from R&D pilot lines to higher-volume production or transfer to external manufacturing partners.

Skills & tools

• Flip chip bonding and thermocompression bonding
• UBM (Under Bump Metallization) stack design and deposition
• MEMS fabrication and integration techniques
• Back-end semiconductor process flow development
• Superconducting qubit hardware architecture
• RF and microwave engineering principles
• Cryogenic packaging design (thermal, mechanical, magnetic)
• Failure analysis (SEM, X-ray, C-SAM, electrical probing)
• Statistical Process Control (SPC) and Design of Experiments (DoE)
• Cleanroom processing (lithography, etch, deposition, metrology)

Practical notes

• The compensation package features a competitive base salary supplemented by a standard 8% holiday allowance paid annually.
• Benefits encompass a comprehensive pension plan with coverage options for partners and dependents, a dedicated personal budget for continuous learning and professional development, and a flexible hybrid working arrangement.
• An open vacation policy is in place, allowing employees to manage their time off responsibly in alignment with project demands.
• Applicants should be aware that a pre-employment screening process may be conducted as a condition of the offer.
• QuantWare actively encourages applications from diverse backgrounds and specifically welcomes female talent to apply, even if they do not satisfy every single criterion listed in the requirements section.

META

Company: Quantware

Title: Advanced Packaging Lead

Listed

location: Delft

Job type: full_time