Digital Verification Engineer

About the role

Neuralink is on the cutting edge of brain-computer interface technology, creating devices that facilitate a bi-directional connection with the brain. This innovative technology aims to restore movement to individuals with paralysis, provide sight to the visually impaired, and redefine human interaction with digital environments. We are seeking a Digital Verification Engineer to join our System-on-Chip (SoC) department within the Implant Team. This position presents a unique opportunity to contribute significantly to the development of advanced brain-computer interfaces, focusing on high-throughput, low-power digital signal processing (DSP). Our team comprises exceptional engineers dedicated to pushing the boundaries of current technology and shaping the future.

Key facts

What you'll do

• Design and execute verification plans for complex digital systems, ensuring that they meet the required specifications and performance metrics.
• Develop and maintain test benches for System-on-Chip (SoC) projects, focusing on high-performance and low-power applications.
• Collaborate closely with architecture and design teams to understand system requirements and translate them into effective verification strategies.
• Automate verification flows using scripting languages such as Python, Perl, Makefile, Tcl, and UNIX shell to enhance efficiency and reduce manual effort.
• Conduct code coverage analysis and set up regression tests to ensure comprehensive verification of design changes.
• Utilize SystemVerilog for functional modeling and logic verification, contributing to the overall quality and reliability of the digital modules.
• Engage in formal verification processes to validate designs against specifications, ensuring robustness and correctness.
• Participate in lab activities, including system bring-up, diagnostic writing, and debugging, to support the hardware verification process.
• Work with industry-standard tools for low-power design simulation and verification, ensuring designs meet power efficiency requirements.
• Collaborate with cross-functional teams to troubleshoot and resolve issues that arise during the verification process.
• Document verification processes and results, providing clear communication of findings to stakeholders.
• Stay updated with industry trends and advancements in ASIC design and verification methodologies to continuously improve team practices.

Requirements

• A minimum of three years of experience in digital ASIC verification, demonstrating a solid understanding of design and verification principles.
• Proficiency in SystemVerilog, with a strong focus on its application in digital verification.
• Experience in developing automation scripts and flows using languages such as Python, Perl, Makefile, Tcl, and UNIX shell.
• Knowledge of code coverage techniques and regression testing methodologies.
• Familiarity with complex digital systems, including architecture, microarchitecture, RTL, verification, and physical design.
• Hands-on experience in building test benches, conducting testing, and debugging for complex SoC projects.
• Understanding of formal verification techniques and their application in ASIC design.
• Experience with low-power design simulation and verification, including knowledge of IEEE-1801 (UPF) based design flows.
• Strong background in verification methodologies, particularly UVM (Universal Verification Methodology).
• Knowledge of ARM and RISC-V processor architectures and AMBA bus protocols.
• Familiarity with power-aware verification processes and methodologies.
• Experience with FPGA and emulation for hardware verification purposes.

Nice to have

• Prior experience in functional modeling and logic verification using SystemC/C++.
• Exposure to low-power formal verification flows, enhancing the efficiency of design validation.
• Experience with lab system bring-up, including writing diagnostics and performing lab debugging.
• Knowledge of industry-standard tools and practices for digital design and verification.
• A background in machine learning or artificial intelligence applications in digital systems could be advantageous.

Skills & tools

• Proficient in SystemVerilog and related verification methodologies.
• Strong programming skills in Python, Perl, Makefile, Tcl, and UNIX shell for automation tasks.
• Familiarity with design simulation tools and environments for ASIC verification.
• Knowledge of digital signal processing concepts and their application in SoC design.
• Experience with lab equipment and diagnostic tools for hardware testing and validation.

Practical notes

Neuralink values its employees and offers a comprehensive benefits package that includes competitive salaries, equity compensation in the form of Restricted Stock Units (RSUs), and a range of health benefits. The expected salary for this position ranges from $131,000 to $243,000, depending on individual skills, experience, and education. Full-time employees also enjoy additional benefits such as paid holidays, commuter perks, meals, a 401(k) plan, parental leave, and flexible time off. This role provides a unique opportunity to work alongside some of the brightest minds in technology and make a tangible impact on the future of human-computer interaction. If you are passionate about pushing the boundaries of technology and eager to contribute to groundbreaking advancements, we encourage you to apply.