Digital ASIC Designer

About the role

Position: Radiation-Tolerant Microcontroller ASIC Design Engineer

CERN's EP-ESE-ME section invites applications for a specialized role focused on the development of a radiation-tolerant microcontroller Application-Specific Integrated Circuit (ASIC). This initiative supports critical systems within future particle physics detectors and accelerator complexes, where operational resilience is paramount. The position operates within the established CERN SOCRATES (System-On-Chip Radiation-Tolerant Ecosystem) framework, utilizing an open-source RISC-V processing core as its foundation.

The successful candidate will engage in the complete project lifecycle. Responsibilities encompass the translation of high-level detector and accelerator requirements into precise technical specifications. This involves defining the system architecture, selecting and configuring the appropriate RISC-V core, and driving the design, integration, and rigorous validation of the microcontroller ASIC. The implementation target is 65 nm or 28 nm CMOS technology.

A core component of the role is the application of advanced fault-tolerant methodologies. The engineer will integrate techniques such as triple modular redundancy (TMR) and single-event upset (SEU) mitigation strategies. Participation extends across the entire verification spectrum, from Register-Transfer Level (RTL) development and simulation through to physical implementation and final tapeout. Post-fabrication activities are equally critical, involving test procedures, electrical characterization, and validation to ensure the ASIC meets its stringent performance and reliability objectives.

Key Responsibilities

• Investigate the specific requirements of CERN's accelerator and detector systems to formulate the technical blueprint for the ASIC.
• Lead the architectural definition and design of a radiation-hardened microcontroller ASIC, selecting the optimal RISC-V core configuration.
• Integrate and verify peripheral IP blocks within the CERN SOCRATES framework to ensure functional correctness.
• Implement fault-tolerant design principles, including TMR and SEU hardening, throughout the design flow.
• Execute a comprehensive verification strategy, progressing from RTL coding to physical sign-off.
• Collaborate closely with physical implementation teams to guide the ASIC through fabrication.
• Participate in post-silicon testing, characterization, and final validation activities.
• Provide technical guidance for firmware development, ensuring compatibility with the microcontroller core and its peripherals.

Professional Profile

Candidates must demonstrate a robust background in digital design engineering. A minimum educational requirement is a Master's degree complemented by 2 to 6 years of relevant professional experience. Alternatively, a PhD is acceptable with no more than 3 years of experience following graduation.

• Expertise in digital logic design, specifically using Verilog or SystemVerilog for RTL development.
• Mastery of the digital ASIC design flow, encompassing synthesis, place-and-route, timing closure, and sign-off procedures.
• Foundational knowledge of RISC-V architecture and its associated software development environment.
• Practical experience with microcontroller-based embedded systems, including firmware coding in C and peripheral interface management.
• Proficiency in scripting and automation, with Python being a primary asset.
• Adeptness in a Linux/Unix-based working environment.

Position Requirements

• Nationality must align with a CERN Member or Associate Member State.
• Possess a professional electronics engineering background.
• Hold either a Master's degree with 2-6 years of post-graduation experience or a PhD with no more than 3 years of post-graduation experience.
• Have no prior history of a CERN fellowship or graduate contract.
• Demonstrate fluency in spoken and written English, with a commitment to learning French.
• Exhibit the capacity to work autonomously while contributing effectively within a diverse, multidisciplinary team.

Compensation and Benefits

Successful applicants will receive a monthly stipend ranging from 6372 to 7004 Swiss Francs, tax-free, based on qualifications. The position includes 30 days of paid annual leave, plus an additional 2 weeks for seasonal closure. Comprehensive health insurance coverage is provided for the employee, spouse, and children, along with membership in the CERN Pension Fund. Relocation support, including an installation grant and travel expense coverage, may be available depending on individual circumstances. The contract offers a potential extension up to 36 months and includes opportunities for on-the-job and formal training, such as language classes.

Field of Work

Electrical or Electronics Engineering

Job Reference

EP-ESE-ME-2026-134-GRAP

Location

Geneva, Switzerland

Engagement

Full-time

Working Hours

40 hours per week

Target Start Date

01 October 2026

Job Flexibility

Fully Onsite

Overview

CERN is the European Organization for Nuclear Research, where science pushes boundaries. We unite a diverse community of professionals to explore fundamental questions and drive innovation. If you are eager to contribute to groundbreaking research using current technology, this is your opportunity.