Senior Emulation Engineer

About the role

You will set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu. You will bring up designs on the emulator, resolving compile, elaboration, capacity, partitioning, and design-mapping issues. You will build and maintain regression flows, optimizing compile time, run time, throughput, and capacity utilization. You will support HW/SW co-verification and pre-silicon software bring-up for firmware, drivers, runtime, and OS. You will optimize on-emulator debug involving waveform capture, triggers, and visibility, driving fast root-cause analysis across HW and SW. You will verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads. You will partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.

Key facts

What you'll do

• Set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu.
• Bring up designs on the emulator, resolving compile/elaboration, capacity/partitioning, and design-mapping issues.
• Build and maintain regression flows, optimizing compile time, run time, throughput, and capacity utilization.
• Support HW/SW co-verification and pre-silicon software bring-up-firmware, drivers, runtime, and OS.
• Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.
• Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.
• Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.
• Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.
• Build automation, scripting, and CI hooks for compile and regression pipelines.
• You will Contribute to FPGA prototyping, pre-silicon validation, and post-silicon debug.
• Apply modern tools, including AI-assisted verification and debug, to improve productivity, quality, and coverage.
• Contribute to a culture of technical excellence and continuous improvement.

Requirements

• Support HW/SW co-verification and pre-silicon software bring-up-firmware, drivers, runtime, and OS.
• Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.
• Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.
• Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.
• Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.
• Build automation, scripting, and CI hooks for compile and regression pipelines.
• You need Contribute to FPGA prototyping, pre-silicon validation, and post-silicon debug.
• Apply modern tools, including AI-assisted verification and debug, to improve productivity, quality, and coverage.

Practical notes

Note: Set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu.

Bring up designs on the emulator, resolving compile/elaboration, capacity/partitioning, and design-mapping issues.

Build and maintain regression flows, optimizing compile time, run time, throughput, and capacity utilization.

Support HW/SW co-verification and pre-silicon software bring-up-firmware, drivers, runtime, and OS.

Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.

Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.

Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.

Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.

Build automation, scripting, and CI hooks for compile and regression pipelines.

For , Contribute to FPGA prototyping, pre-silicon validation, and post-silicon debug.

Apply modern tools, including AI-assisted verification and debug, to improve productivity, quality, and coverage.

Contribute to a culture of technical excellence and continuous improvement.

Support HW/SW co-verification and pre-silicon software bring-up-firmware, drivers, runtime, and OS.

Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.

Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.

Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.

Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.

You will use go.

Note: Set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu.

Bring up designs on the emulator, resolving compile, elaboration, capacity, partitioning, and design-mapping issues.

Build and maintain regression flows, optimizing compile time, run time, throughput, and capacity utilization.

Support HW/SW co-verification and pre-silicon software bring-up-firmware, drivers, runtime, and OS.

Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.

Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.

Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.

Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.

Build automation, scripting, and CI hooks for compile and regression pipelines.

For , Contribute to FPGA prototyping, pre-silicon validation, and post-silicon debug.

Apply modern tools, including AI-assisted verification and debug, to improve productivity, quality, and coverage.

Contribute to a culture of technical excellence and continuous improvement.

Support HW/SW co-verification and pre-silicon software bring-up-firmware, drivers, runtime, and OS.

Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.

Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.

Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.

Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.

You will use go.

Note: Set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu.

Bring up designs on the emulator, resolving compile, elaboration, capacity, partitioning, and design-mapping issues.

Build and maintain regression flows, optimizing compile time, run time, throughput, and capacity utilization.

Support HW/SW co-verification and pre-silicon software bring-up-firmware, drivers, runtime, and OS.

Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.

Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.

Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.

Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.

Build automation, scripting, and CI hooks for compile and regression pipelines.

For , Contribute to FPGA prototyping, pre-silicon validation, and post-silicon debug.

Apply modern tools, including AI-assisted verification and debug, to improve productivity, quality, and coverage.

Contribute to a culture of technical excellence and continuous improvement.

Support HW/SW co-verification and pre-silicon software bring-up-firmware, drivers, runtime, and OS.

Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.

Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.

Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.

Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.

You will use go.

Note: Set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu.

Bring up designs on the emulator, resolving compile, elaboration, capacity, partitioning, and design-mapping issues.

Build and maintain regression flows, optimizing compile time, run time, throughput, and capacity utilization.

Support HW/SW co-verification and pre-silicon software bring-up-firmware, drivers, runtime, and OS.

Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.

Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.

Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.

Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.

Build automation, scripting, and CI hooks for compile and regression pipelines.

For , Contribute to FPGA prototyping, pre-silicon validation, and post-silicon debug.

Apply modern tools, including AI-assisted verification and debug, to improve productivity, quality, and coverage.

Contribute to a culture of technical excellence and continuous improvement.

Support HW/SW co-verification and pre-silicon software bring-up-firmware, drivers, runtime, and OS.

Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.

Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.

Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.

Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.

You will use go.

Note: Set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu.

Bring up designs on the emulator, resolving compile, elaboration, capacity, partitioning, and design-mapping issues.

Build and maintain regression flows, optimizing compile time, run time, throughput, and capacity utilization.

Support HW/SW co-verification and pre-silicon software bring-up-firmware, drivers, runtime, and OS.

Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.

Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.

Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.

Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.

Build automation, scripting, and CI hooks for compile and regression pipelines.

For , Contribute to FPGA prototyping, pre-silicon validation, and post-silicon debug.

Apply modern tools, includ