Custom Circuit Design (Sr. Staff

About the role

The posting lists Bangalore. Lead architecture design optimization of high-performance low-power standard cells for advanced process technologies focusing PPA. Design optimize transistor-level circuits including latches flip-flops multiplexers AOI OAI XOR XNOR encoders decoders level shifters arithmetic cells other complex sequential combinational logic. Architect develop advanced arithmetic building blocks including adders multipliers integer floating-point MAC units for high-performance compute applications. Develop schematics using Cadence Virtuoso and perform post-layout validation through parasitic extraction using StarRC or Quantus.

Key facts

What you'll do

• Lead architecture design optimization of high-performance low-power standard cells for advanced process technologies focusing PPA.
• Design optimize transistor-level circuits including latches flip-flops multiplexers AOI OAI XOR XNOR encoders decoders level shifters arithmetic cells other complex sequential combinational logic.
• Architect develop advanced arithmetic building blocks including adders multipliers integer floating-point MAC units for high-performance compute applications.
• Develop schematics using Cadence Virtuoso and perform post-layout validation through parasitic extraction using StarRC or Quantus.
• Perform circuit verification across all PVT corners using HSPICE PrimeSim XA or Spectre ensuring robust functionality timing and power performance.
• Drive statistical verification using Monte Carlo methodologies and advanced variation analysis with Solido Spectre FMC or equivalent tools.
• Own reliability sign-off activities including electromigration IR-drop self-heating BTI HCI aging analysis while ensuring ESD and latch-up robustness.
• Drive low-power circuit innovations through multi-Vt optimization leakage reduction power gating retention strategies isolation cells and power-intent-aware design methodologies.
• Collaborate closely with custom layout teams to optimize layouts for Layout Dependent Effects manufacturability coloring compliance matching and pin accessibility.
• Partner with Characterization Physical Design STA CAD and Product Engineering teams to ensure successful library development silicon readiness and production-quality deliverables.
• Drive design methodology improvements automation initiatives and technical best practices across the circuit design organization.
• Mentor engineers and provide technical leadership in circuit design methodology development and advanced technology enablement.

Requirements

• + years of experience in custom digital circuit design standard cell development or memory circuit design.
• Strong expertise in transistor-level CMOS circuit design for advanced technology nodes.
• You need Proven experience designing optimizing high-performance low-power standard cell libraries.
• Deep understanding of advanced process technologies including FinFET and Gate-All-Around GAA.
• Extensive experience with circuit simulation tools such as HSPICE PrimeSim XA or Spectre.
• You need Experience with parasitic extraction using StarRC or Quantus.
• Strong knowledge of statistical verification Monte Carlo analysis and variation-aware circuit design.
• Experience performing reliability verification including electromigration IR-drop aging self-heating and silicon robustness analysis.
• Demonstrated ability to drive complex technical projects from concept through silicon.

Nice to have

• Master's or Ph.D. in Electrical Electronics Engineering or a related discipline.
• Strong understanding of digital circuit architecture standard cell design and advanced flip-flop architectures.
• Experience with standard cell characterization using Liberate or PrimeLib including Liberty .lib generation and validation.
• Good understanding of Static Timing Analysis STA Liberty timing models and ASIC sign-off methodologies.
• Familiarity with complete ASIC development flows from circuit design through physical implementation and silicon validation.
• It helps if Experience developing automation using Python Tcl or Perl.
• Track record of leading technical initiatives and mentoring engineering teams.
• It helps if Experience with SRAM peripheral circuit design.
• It helps if Knowledge of UPF and power intent methodologies.
• Exposure to layout optimization techniques including LDE coloring matching and pin accessibility.
• It helps if Familiarity with silicon bring-up characterization and production support.
• It helps if Experience driving design methodology improvements and EDA automation.
• It helps if Strong technical leadership mentoring communication and cross-functional collaboration skills.
• Passion for innovation and delivering high-quality silicon under aggressive product schedules.
• Background in custom digital CMOS circuit design standard cell library architecture design and optimization arithmetic circuit design low-power circuit design and optimization advanced-node technologies including FinFET and GAA library characterization and timing model development or cross-functional silicon development in advanced semiconductor environments.

Skills & tools

You will use Cadence Virtuoso. You will use HSPICE. You will use PrimeSim XA. You will use Spectre. You will use StarRC. You will use Quantus. You will use Solido. You will use Python. You will use Tcl. You will use Perl.