SoC Debug and Trace Architect

About the role

Tenstorrent is pioneering the development of next-generation AI hardware and RISC-V CPUs. The SoC Debug and Trace Architect will play a critical role in ensuring the reliability and stability of these advanced compute platforms. This position focuses on diagnosing intricate technical problems across the entire technology stack, from silicon and firmware to software. You will own the end-to-end debug flow for complex system-level issues, requiring a methodical and creative approach to isolating faults in a high-performance AI environment. As the central technical authority for trace and debug strategy, your work will directly influence product stability, performance, and timeline de-risking. Success in this role demands close collaboration with cross-functional teams to drive problems to resolution efficiently.

About the role

• Act as the central technical authority for trace and debug strategy on next-generation silicon, shaping the overall approach to failure analysis.
• Own the end-to-end debug flow for complex system issues spanning hardware, firmware, and software layers.
• Drive problem resolution through rigorous analysis, directly impacting the stability and performance of critical AI hardware platforms.
• Champion best practices for trace and debug across the organization to elevate engineering maturity and methodology.
• Collaborate closely with cross-functional partners to align on objectives, timelines, and solution implementation.
• De-risk the product timeline by identifying and resolving complex technical issues early in the development flow.

What you'll do

• Lead post-silicon debug efforts for AI accelerator platforms, investigating hardware and firmware failures across silicon, boards, and entire systems.
• Identify root causes of issues spanning power, thermal management, GDDR memory subsystems, PCIe interfaces, Ethernet/SerDes links, NoC interconnects, and embedded firmware.
• Create diagnostic tools and automation frameworks using Python and C to accelerate failure analysis and improve debug efficiency.
• Utilize lab instruments such as protocol analyzers, logic analyzers, and oscilloscopes to troubleshoot complex system-level errors.
• Evaluate register states, board schematics, telemetry data, and firmware performance to resolve intricate hardware problems.
• Develop and maintain comprehensive, reusable debug methodologies that can be applied across projects and teams.
• Drive the creation of test procedures that validate hardware fixes and prevent regression in future silicon revisions.
• Work closely with validation, ASIC, software, and firmware teams to ensure alignment on debug goals, timelines, and solutions.
• Document findings thoroughly and communicate complex technical issues clearly and effectively to diverse stakeholders.
• Champion trace and debug best practices to improve the overall engineering maturity of the organization.

Requirements

• Proven experience with post-silicon bring-up and hardware debug for SoC, CPU, or ASIC systems in a high-performance computing context.
• Strong understanding of microarchitecture and processor architectures, specifically RISC-V, ARM, or x86 implementations.
• Familiarity with trace and debug methodologies and tools, including iJTAG and related standards.
• Demonstrated ability to perform root-cause analysis across hardware, software, and firmware domains simultaneously.
• Experience building scalable debug methodologies and automation frameworks within a lab environment.
• Proven ability to work effectively across validation, ASIC, software, and firmware teams in a cross-functional setting.
• Strong understanding of digital design concepts, signal integrity issues at the board level, and electrical behavior of memory interfaces like GDDR/DDR.
• Deep knowledge of protocols and interfaces such as PCIe, Ethernet, and SerDes, including their physical layer and link layer behavior.
• Willingness to adhere to strict data security protocols when handling sensitive debug information and export-controlled technology.
• Ability to obtain necessary citizenship or residency status, or export license approval, as required by U.S. Export Administration Regulations.

Skills & tools

• Expert-level proficiency in Python for automation and diagnostic tool development.
• Strong C programming skills for low-level firmware interaction and debug infrastructure.
• Hands-on experience with iJTAG and trace/debug infrastructure.
• Practical experience using oscilloscopes for signal measurement and analysis.
• Demonstrated skill with logic analyzers for capturing and analyzing digital signals.
• Experience with protocol analyzers to inspect and validate communication bus transactions.
• Deep understanding of RISC-V, ARM, or x86 processor architectures and their debug architectures.
• Knowledge of GDDR, DDR memory systems and their testing methodologies.
• Comprehensive understanding of PCIe protocol stack, configuration, and debugging.
• Experience with Ethernet and SerDes interfaces, including link training and troubleshooting.

Practical notes

This role is open to various experience levels, and final compensation will be determined based on the assessed level during the interview process. Employment is contingent upon the candidate being eligible to access U.S. export-controlled technology under U.S. Export Administration Regulations. Candidates may be required to provide proof of citizenship or residency status, or obtain export license approval before commencing employment.