RISC-V CPU Microarchitecture

About the role

Tenstorrent is building high-performance AI platforms by developing custom RISC-V CPU technology from the ground up. We are looking for engineers to own RTL design and microarchitecture specifications for our next-generation processor units. This role is open to various seniority levels and focuses on optimizing power, performance, and area through advanced design practices. You will be responsible for defining the foundational behavior of execution units that drive artificial intelligence workloads. Your analysis will directly influence how instructions are processed and how resources are utilized at the silicon level. This position requires a deep partnership with system architects to ensure that the microarchitecture aligns with product vision. You will play a key role in translating high-level requirements into precise implementation strategies that can be verified in hardware.

Key facts

What you'll do

• Author microarchitecture specifications for CPU units including branch predictors, rename logic, instruction scheduling, and vector execution.
• Manage the full design lifecycle for CPU core units, covering RTL coding, verification, and PPA closure.
• Develop strategies for unit verification and perform rigorous analysis to meet performance targets.
• Integrate AI-driven tools into the design workflow to increase development efficiency.
• Provide technical mentorship to junior team members based on your level of experience.
• Define the interface protocols that allow CPU cores to communicate with memory and I/O subsystems.
• Analyze performance bottlenecks and implement microarchitectural changes to reduce latency and increase throughput.
• Collaborate with compiler teams to ensure that the instruction set architecture is supported effectively in software.
• Evaluate emerging RISC-V extensions and assess their applicability to future product generations.
• Conduct design reviews and code inspections to maintain high standards of quality and readability.
• Troubleshoot complex functional issues that arise during simulation or on emulation hardware.
• Document design decisions and rationale to ensure long-term maintainability and knowledge transfer.
• Partner with validation engineers to develop testbenches that comprehensively cover architectural features.
• Lead the optimization of power consumption without sacrificing critical performance metrics.

Requirements

• Bachelor, Master, or PhD in Computer Science, Electrical Engineering, Computer Engineering, or a related discipline.
• Demonstrated history of building high-performance RTL for architectures such as RISC-V, Arm, x86, SPARC, or POWER.
• Expertise in hardware description languages including SystemVerilog, Verilog, or VHDL.
• Strong grasp of CPU microarchitecture and the trade-offs involved in PPA.
• Comprehensive knowledge of verification methodologies, including formal methods, simulation, and checker development.
• Ability to communicate complex technical details and collaborate across multidisciplinary teams.
• U.S. citizenship, permanent residency, or specific license approval from the U.S. Commerce Department due to export control regulations.
• Eligibility to access technology controlled by U.S. export laws as a condition of employment.
• Minimum educational attainment must be a Bachelor, Master, or PhD from an accredited institution.
• Proven track record of delivering production-level hardware designs that meet rigorous specifications.
• Experience with advanced CPU design techniques such as out-of-order execution, speculative execution, or pipeline optimization.
• Solid understanding of how microarchitectural choices impact power dissipation and thermal characteristics.
• Familiarity with standard hardware verification flows and the use of constrained-random simulation.
• Commitment to maintaining a high level of accuracy in documentation and specification writing.
• Willingness to work within the constraints of U.S. government regulations related to sensitive technologies.

Nice to have

• Working knowledge of the RISC-V architecture, specifically the V-extension.

Practical notes

Employment is contingent upon your eligibility to access technology controlled by U.S. export laws. Because this role involves access to sensitive systems, candidates may need to be U.S. citizens, permanent residents, or obtain specific license approval from the U.S. Commerce Department. Offers are determined based on individual skills, education, experience, and location, and may be adjusted to match the appropriate seniority level identified during the interview process.