Sr Staff Engineer, SoC RTL Design

About the role

Tenstorrent is building high-performance AI hardware by integrating custom RISC-V CPUs with advanced silicon architectures. We are seeking a digital design expert to architect and implement the RTL for our next generation of compute platforms. In this role, you will own the architectural definition and implementation of critical SoC modules that form the backbone of our AI accelerators. You will be responsible for translating high-level system specifications into robust, synthesizable RTL that meets stringent performance and power targets. A significant portion of your work will involve designing and optimizing the interaction between compute, memory, and interconnect subsystems at the register-transfer level. You will lead design reviews and make foundational choices that shape the scalability and reliability of the overall silicon strategy. This position requires a deep partnership with validation and physical design teams to ensure that the hardware is not only correct but also manufacturable and testable. Your contributions will directly influence the capabilities and efficiency of the next generation of Tenstorrent compute products.

Key facts

What you'll do

• Architect and implement complex RTL for custom IP blocks and SoC components using Verilog or VHDL.
• Drive design decisions that maximize performance, power efficiency, and area utilization for memory and interconnect heavy blocks.
• Lead the development and integration of verification components within UVM environments to ensure functional correctness.
• Collaborate closely with physical design teams to analyze synthesis results and resolve timing closure challenges early in the flow.
• Evaluate and adopt new methodologies for FPGA prototyping to accelerate bring-up and system-level validation.
• Partner with architecture teams to define microarchitectural specifications that align with product requirements and technology constraints.
• Guide junior engineers through code reviews, best practices, and the application of advanced RTL coding styles.
• Support the creation and execution of test plans that validate hardware behavior against formal models and emulation results.
• Implement low-power optimization strategies and clock gating techniques to meet aggressive power budgets.
• Troubleshoot complex functional coverage gaps and regression failures to improve sign-off quality.
• Interface with internal stakeholders to translate abstract system features into concrete hardware implementation plans.
• Contribute to the development and maintenance of ASIC design flows and supporting infrastructure.
• Mentor peers on emerging verification flows and synthesis constraints relevant to our multi-die and chiplet-based designs.
• Ensure all deliverables comply with export control regulations and internal security policies governing sensitive information.

Requirements

• Demonstrate proficiency in RTL development using Verilog or VHDL with a strong portfolio of production-level code.
• Bring experience with full ASIC design flows from specification through to tapeout and post-silicon validation.
• Show a proven ability to optimize designs for power, performance, and area in complex digital systems.
• Possess a deep understanding of computer architecture and the microarchitectural details of compute and memory systems.
• Exhibit strong communication skills for technical planning, specification definition, and rigorous peer reviews.
• Have a history of working with on-chip fabric and interconnect designs to integrate diverse IP blocks efficiently.
• Display meticulous attention to detail to ensure signal integrity, protocol compliance, and timing robustness.
• Commit to working collaboratively in a fast-paced, cross-functional environment that values innovation and ownership.

Nice to have

• Prior experience working with on-chip fabric and interconnect designs.

Practical notes

Employment is contingent upon your eligibility to access technology controlled by United States export laws. Because this role involves access to sensitive information, you must be able to comply with U.S. Export Administration Regulations, which may require citizenship, permanent residency, or specific government license approval. We offer a competitive compensation and benefits package. Candidates of varying seniority levels are encouraged to apply, as final offers will be adjusted based on the evaluation during the interview process.