Network Engineer - ML Infrastructure

About the role

SpaceXAI is developing advanced AI systems to expand human knowledge and interpret the universe. We are seeking a technical expert to build and manage the high-speed network fabric that supports our large-scale training and inference clusters. The role owner is responsible for architecting the physical and logical infrastructure that connects thousands of accelerators with minimal latency and maximum throughput. This position requires deep collaboration with hardware engineers, software teams, and external partners to define and deliver the next generation of AI networking. You will validate designs through simulation and real-world testing to ensure resilience at planetary scale. The ideal candidate treats the network not as a commodity but as a first-class compute primitive. Decisions you make will directly influence the speed at which humanity-scale models are trained and deployed. You are expected to operate at the intersection of physics, economics, and reliability.

Key facts

What you'll do

• Architect and validate high-speed copper and optical connectivity for clusters exceeding 100,000 GPUs, ensuring deterministic latency and lossless transmission under extreme load.
• Manage vendor relationships and product qualification for 1.6T hardware, including AEC and pluggable transceivers like DR4/8 and FR4, to guarantee interoperability and performance.
• Research the implementation of LPO and LRO technologies within our network to reduce protocol overhead and improve end-to-end throughput.
• Assess early-stage near-packaged and co-packaged engines for GPU and switch integration, analyzing thermal, power, and signal integrity impacts at the module level.
• Explore new interconnect methods such as microLED, VCSEL, and THz radio to enhance network reliability and cost-efficiency beyond traditional fiber systems.
• Engage with silicon photonics foundries, DSP providers, and cable manufacturers to guide product roadmaps and influence component-level specifications.
• Partner with ML training teams to convert communication patterns into specific topology and optical requirements, aligning network behavior with algorithmic needs.
• Conduct end-to-end fabric performance simulations to predict bottlenecks, contention, and failure modes before hardware deployment.
• Lead root cause analysis and corrective measures for production interconnect issues using fleet-wide telemetry and trace data.
• Develop internal automation for diagnostics, health monitoring, and qualification pipelines to reduce manual overhead and accelerate feedback.
• Monitor industry standards and emerging developments like 448G SerDes, hollow-core fiber, and ring resonators to maintain technological leadership.
• Define test methodologies and acceptance criteria for new network components, ensuring rigorous validation before mass deployment.
• Optimize spectral efficiency and power consumption across the fabric without compromising availability or scalability.
• Serve as the primary technical authority on network matters for executive, legal, and operational stakeholders.

Requirements

• Minimum of 8 years of experience in high-speed copper and optical interconnects, either in module design or hyperscale data center operations, with a proven track record of delivering reliable solutions.
• Master degree or PhD in Physics, Photonics, or Electrical Engineering, demonstrating deep theoretical and practical knowledge of wave and signal propagation.
• Proficiency in PAM4 SerDes performance, including crosstalk, jitter, and equalization, with hands-on experience characterizing eye diagrams and bit error rates.
• Operational knowledge of Retimers, FEC, Drivers, and TIAs, including their impact on link budget and system-level margins.
• Expertise in optical link budget analysis, including TDECQ, OMA, Tcode, and stressed receiver sensitivity, to ensure compliance with demanding AI workloads.
• Familiarity with transceiver components such as SiPh PICs, CW lasers, EML, DSP, and passive subassemblies, including failure modes and mitigation strategies.
• Understanding of signal integrity, power, thermal, and mechanical constraints in high-density hardware, enabling holistic design trade-off analysis.
• Knowledge of SiPh reliability testing, yield improvement, and design processes, with experience correlating accelerated tests to field lifetime.
• Experience with CPO technology risks and challenges, including clock recovery, skew management, and thermal drift in dense arrays.
• Familiarity with the global supply chain, including ODMs, CMs, and subcomponent manufacturers, to navigate procurement and logistics constraints.

Skills & tools

• OIF CMIS for module-level interoperability and compliance verification.
• IEEE standards governing physical layer protocols, timing, and electrical interfaces.
• TFLN platforms for modeling photonic networks and exploring alternative architectures.
• 448G SerDes specifications and implementation details for next-generation serializer-deserializer blocks.
• SiPh PICs design tools and characterization methodologies for integrated photonic circuits.
• 1.6T products roadmap and performance envelopes to guide architecture planning.
• AEC/ACC/CPC compliance frameworks for automotive and aerospace relevant variants.
• FRO/LRO/TRO/LPO/AOC/CPO feature sets to evaluate trade-offs between reach, power, and complexity.

Practical notes

Total compensation includes base salary, equity, medical, dental, and vision insurance, 401(k) plan, and life/disability insurance. SpaceXAI is an equal opportunity employer.