Signal Integrity Engineer

About the role

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. As a Signal Integrity Engineer on Starlink's Payload Engineering team, you will own the signal integrity of critical high-speed hardware throughout the entire lifecycle of satellite payloads. Your responsibilities will span from silicon architecture evaluation and package performance assessment to channel stack-up selection and rigorous PCB layout oversight. You will drive the troubleshooting, characterization, qualification, and debug processes for hardware at every phase of its operational life. In this role, you will define the design, analysis, and verification methodologies that the Starlink team uses to develop reliable hardware systems. You are expected to solve complex problems independently and propagate your expertise and techniques across the Starlink engineering organization.

Key facts

What you'll do

• Specify, design, simulate, verify, qualify, define production screens for, and generally troubleshoot SI aspects of advanced satellite hardware, such as wireline and electro-optical communication systems utilizing cutting edge SERDES, DSPs, retimers, and optoelectronics operating at data rates from 10 to 112+ Gbps.
• Specify, design, simulate, verify, qualify, define production screens for, and generally troubleshoot SI aspects of advanced satellite hardware, such as high-speed and high-bandwidth memory interfaces including DDR4, LPDDR5, GPDDR6, QSPI NOR, and eMMC.
• Work alongside RF engineers, antenna engineers, ASIC engineers, packaging engineers, mechanical engineers, thermal engineers, software engineers, supply chain, and production engineers to architect new products which will employ novel channels, interfaces, and power delivery strategies.
• Derive top level specifications for PCB materials and channel subcomponents to ensure performance targets are met across the entire satellite payload.
• Design and optimize transition structures for the entire channel from die bump to die bump, minimizing reflections and ensuring robust signal propagation.
• Root cause, fix, and validate issues identified during PCB manufacturing, PCBA test, or satellite integration to meet stringent reliability requirements.
• Define best practices, simulation workflows, test methodologies, signoff criteria, and lab equipment needs for all signal integrity requirements on Starlink satellite payloads.
• Collaborate with cross-functional teams to translate system-level requirements into hardware-level SI constraints and verification plans.
• Mentor and train other engineers on SI analysis techniques, tools, and methodologies to elevate the overall capability of the Starlink program.
• Drive the development and maintenance of internal documentation, models, and procedures to ensure consistency and repeatability in SI design and validation.
• Participate in the development and execution of test plans that validate SI performance under real-world conditions, including thermal, vibration, and electromagnetic environments.
• Support the development of new product introductions by providing SI input during concept, architecture, and design freeze stages.
• Act as the SI subject matter expert for payload hardware, interfacing with external partners and suppliers as required to ensure design integrity.
• Continuously evaluate emerging technologies and techniques to improve the performance, cost, and manufacturability of SI solutions.

Requirements

• Hold a Bachelor's degree in electrical engineering, computer engineering, or physics as a fundamental requirement for the role.
• Possess 1+ years of industry experience designing circuits, electronic products, or hardware, where internship, co-op, and research/lab experience is accepted toward this total.
• Demonstrate 1+ years of hands-on experience using at least one of the major 3D electromagnetic simulation tools and high-speed digital channel simulators such as CST, HFSS, or ADS.
• Show 1+ years of research or industry experience focused on high-speed digital design principles and implementation practices.
• Exhibit the ability to work effectively in a fast-paced, deadline-driven engineering environment where priorities can shift rapidly.
• Demonstrate strong written and verbal communication skills necessary for documenting designs and coordinating with multidisciplinary teams.
• Apply critical thinking and problem-solving skills to diagnose complex signal integrity issues and develop robust engineering solutions.
• Maintain attention to detail and accuracy when managing design constraints, simulation models, and test results.

Nice to have

• Hold a Master's degree or PhD in electrical engineering, computer engineering with emphasis in electromagnetic theory, transmission line theory, or wireline transceivers.
• Bring 3+ years of electronic product experience designing hardware from initial concept through production release, with a strong emphasis on full life-cycle development rather than incremental updates to legacy hardware.
• Offer 3+ years of experience architecting, implementing, and debugging cutting-edge DSP-based SERDES products, including those operating at 56Gbps, 112Gbps, and 224Gbps across package and PCB interfaces.

Practical notes

This role may involve extended work hours and occasional travel to meet project deadlines or address critical on-site issues. Employment eligibility to work in the United States is required for this position.