Sr. RTL Design Engineer

About the role

SpaceX is building the Starlink satellite constellation to provide global broadband internet. This role focuses on developing custom ASICs for space and ground infrastructure to improve network performance and connectivity. The position sits within the Silicon Engineering team where your work directly influences the throughput and reliability of satellite operations. You will own complex digital logic that bridges high-level architectural concepts to physical implementation. The role demands rigorous analysis of system behavior under orbital and terrestrial constraints. You will be responsible for ensuring that custom hardware meets the stringent demands of launch and deep space conditions. Your contributions will enable faster data routing and more efficient power usage across SpaceX communication platforms.

Key facts

What you'll do

• Investigate architectural trade-offs concerning latency, throughput, and area efficiency for next-generation modules.
• Engineer micro-architectures and author Register Transfer Level code using Verilog or SystemVerilog to meet interface specifications.
• Synthesize and integrate multi-module designs while guaranteeing timing closure and clean gate-level netlists.
• Partner with verification groups to establish test strategies and coverage metrics that validate functional correctness.
• Author timing constraints and support the physical implementation group with static timing analysis and equivalence checking.
• Conduct failure analysis and debug procedures during silicon bring-up to resolve anomalies in hardware behavior.
• Optimize block-level integration to ensure protocol compliance with advanced on-chip network standards.
• Evaluate low-power design strategies and clock domain crossing solutions to enhance signal integrity across voltage islands.
• Utilize scripting capabilities in Python to automate regression tests, data extraction, and reporting workflows.
• Leverage knowledge of standard bus protocols like AXI and AHB to streamline communication between subsystems.
• Assess system-level performance using profiling tools to identify bottlenecks in data movement and storage paths.
• Mentor junior engineers on coding best practices, lint rules, and simulation methodologies to elevate team quality.

Requirements

• Hold a Bachelor degree in electrical engineering, computer engineering, or computer science from an accredited institution.
• Demonstrate a minimum of 5 years of hands-on experience in RTL implementation for digital hardware.
• Exhibit proficiency in writing testable and synthesizable Verilog or SystemVerilog code under tight schedules.
• Show the ability to interpret complex technical documents and translate requirements into register transfer level constructs.
• Prove experience with synchronous design techniques and robust verification methodologies to reduce silicon risk.
• Display strong problem-solving skills when addressing timing violations, metastability, and signal degradation issues.
• Confirm capability to work independently and within cross-functional teams in a fast-paced aerospace environment.
• Confirm eligibility to work in positions requiring U.S. citizenship, permanent residency, refugee, or asylee status due to ITAR regulations.

Nice to have

• Demonstrated success in solving clock domain crossing and power optimization challenges in prior tape-outs.
• Hands-on background in ASIC/SoC system integration with a portfolio of shipped hardware projects.
• Practical experience with embedded CPU subsystems and standard bus protocols like AXI or AHB in real designs.
• Familiarity with high-speed signaling techniques and low-power design methods such as clock gating and power gating.
• Ability to write Python scripts that automate verification flows, regression runs, and data visualization tasks.
• Prior exposure to EDA tools, including HDL simulators, waveform viewers, and linting software for code quality checks.

Skills & tools

• Verilog
• SystemVerilog
• Python
• HDL Simulators
• HDL Lint tools
• AXI/AHB protocols

Practical notes

Salary range: $165,000 to $260,000 per year. Compensation includes potential stock options, long-term cash awards, discretionary bonuses, and an Employee Stock Purchase Plan. Benefits include medical, dental, vision, 401(k), life insurance, disability insurance, paid parental leave, 3 weeks of vacation, 10+ paid holidays, and 5 days of sick leave. Applicants must be able to work weekends or extended hours for mission-critical deadlines. This position is subject to ITAR regulations, requiring candidates to be U.S. citizens, permanent residents, refugees, or asylees.