Manager, ASIC Design Engineering

About the role

This position leads the digital design team for Starshield, a SpaceX initiative focused on government satellite systems for earth observation and communications. You will oversee the full lifecycle of ASIC and FPGA development, from initial architecture to on-orbit operations. The role requires defining the technical vision for complex digital hardware while ensuring alignment with stringent aerospace and defense requirements. You will act as the primary technical authority for all aspects of the ASIC and FPGA design flow. Success in this position depends on your ability to translate high-level mission objectives into concrete silicon implementations. You will be responsible for building a high-performance digital engineering organization capable of delivering reliable hardware in a demanding environment. The position demands deep expertise in managing both the strategic and tactical elements of hardware development. You will drive innovation in digital design to meet the rigorous performance and reliability standards expected by Starshield customers.

Key facts

What you'll do

• Lead a team of engineers in the digital design of ASICs and FPGAs for satellite projects, setting technical direction and ensuring timely execution.
• Manage architectural trade-offs, define system specifications, and coordinate with RFIC and DSP engineers on hardware-software partitioning to optimize system performance.
• Develop micro-architectures and implement RTL using Verilog or System Verilog, ensuring code quality, maintainability, and scalability.
• Deliver synthesis and timing-clean designs integrated at the top level, meeting stringent performance, power, and area targets.
• Collaborate with verification teams to ensure comprehensive design coverage, facilitating a smooth transition from design to verification.
• Provide timing constraints and assist the physical implementation team with synthesis and timing closure, bridging the gap between design and physical realization.
• Support silicon bring-up, validation, and the creation of automated lab test equipment to ensure the hardware functions correctly in the target environment.
• Recruit and mentor engineering staff, fostering a culture of excellence, innovation, and continuous improvement within the digital design team.
• Establish and maintain rigorous design processes and documentation to ensure traceability, repeatability, and compliance with regulatory standards.
• Evaluate and adopt new EDA tools, methodologies, and techniques to improve design productivity and product quality over time.
• Partner with cross-functional teams to identify and resolve complex technical issues that arise during the design and manufacturing phases.
• Ensure all designs comply with relevant safety, reliability, and security standards required for space-based government applications.
• Analyze design metrics and performance data to drive optimization efforts and inform future architectural decisions.
• Represent the digital design function in internal and external technical discussions, communicating status, risks, and solutions effectively.

Requirements

• Bachelor degree in electrical engineering, computer engineering, computer science, or related field.
• 5+ years of experience in ASIC or FPGA development and RTL implementation in a professional engineering environment.
• 2+ years of experience in a direct management or team mentorship role, demonstrating leadership capabilities.
• Must be a U.S. citizen, lawful permanent resident, refugee, or asylee to comply with ITAR regulations.
• Proven ability to manage multiple design projects simultaneously while maintaining a high standard of quality.
• Demonstrated experience with digital design flows, including synthesis, timing analysis, and implementation.
• Strong understanding of digital logic fundamentals, including finite state machines, combinatorial logic, and sequential logic design.
• Familiarity with version control systems and hardware description language best practices is essential for team collaboration.
• Commitment to adhering to SpaceX engineering standards and processes to ensure consistency and reliability.
• Willingness to comply with security protocols and eligibility requirements for handling sensitive aerospace programs.

Nice to have

• Experience with multicore CPU subsystems and embedded processors, enabling more sophisticated system architectures.
• Proficiency in high-speed, low-power design techniques and clock domain crossing, critical for modern digital interfaces.
• Familiarity with standard bus protocols like AXI or AHB, facilitating integration with existing system infrastructure.
• Scripting skills in Python or TCL, enhancing automation and improving design verification efficiency.
• Experience with EDA tools including VCS, Questa, IES, Spyglass, Xilinx Vivado, or Altera Quartus II, reducing the learning curve and accelerating development.

Practical notes

• You may be required to work long hours and weekends to meet project milestones, ensuring critical deadlines are met.
• Travel is required for off-site testing, allowing for direct interaction with hardware and validation activities.
• An active TS-SCI clearance may be required for specific missions; holders receive a 10% salary differential (up to $20,000 annually) once briefed into classified programs.
• Compensation includes potential stock, long-term cash awards, discretionary bonuses, and an Employee Stock Purchase Plan.
• Benefits include medical, vision, dental, 401(k), disability insurance, life insurance, paid parental leave, 3 weeks of vacation, and 10+ paid holidays.
• Subject to pre-employment drug and alcohol testing if working on sensitive missions, ensuring a safe and secure work environment.