EDA Engineer (RFIC Engineering)

About the role

SpaceX is seeking a technical professional to maintain and optimize the integrated circuit design environment for the Starlink satellite program. You will work closely with silicon, verification, and physical design teams to ensure tool reliability and streamline workflows for analog, RF, and mixed-signal projects. In this capacity, you will own the stability and performance of the EDA infrastructure that underpins critical satellite communication hardware development. The ideal candidate will act as a bridge between advanced IC design methodologies and the practical constraints of high-performance computing environments. You will be responsible for transforming complex design requirements into robust, automated technical solutions. This role demands a meticulous problem solver who can anticipate workflow bottlenecks before they impact project timelines. Your contributions will directly influence the efficiency of RFIC engineering teams working on next-generation connectivity systems.

Key facts

What you'll do

• Oversee complex EDA and CAD workflow orchestration, including environment configuration, PDK lifecycle management, and multi-tool simulation support.
• Architect and implement PDK installation frameworks with rigorous version tracking strategies for diverse foundry process technologies.
• Diagnose intricate simulation failures, DRC rule violations, LVS connectivity discrepancies, PEX extraction anomalies, and license allocation conflicts through systematic debugging methodologies.
• Engineer sophisticated automation scripts that enhance log aggregation processes, enforce preflight validation checks, and generate comprehensive regression analysis reports.
• Author and sustain detailed technical documentation and operational runbooks that codify standard design flows for analog, RF, and mixed-signal applications.
• Execute exhaustive QA validation protocols for EDA tool upgrades, software patches, and experimental flow modifications prior to organizational deployment.
• Liaise proactively with IT infrastructure and HPC computing teams to diagnose and eliminate computational resource constraints and scheduling inefficiencies.
• Administer and optimize data management ecosystems including Perforce and Cliosoft implementations for design version control.
• Establish baseline performance metrics for EDA tool suites and drive continuous improvement initiatives across RFIC design pipelines.
• Collaborate with cross-functional engineering teams to translate abstract design requirements into concrete EDA implementation strategies.
• Evaluate emerging verification methodologies and propose integration pathways for advanced design rule checking solutions.
• Mentor junior engineering staff on best practices for IC design environment management and troubleshooting techniques.
• Participate in on-call rotation schedules to provide rapid response for critical EDA infrastructure incidents.
• Contribute to the technical roadmap for EDA tool deployment and process optimization across the RFIC organization.

Requirements

• Hold a Bachelor degree in electrical engineering, computer engineering, or computer science from an accredited institution.
• Demonstrate a minimum of 2 years of professional experience in CAD support, IC design flow development, or physical verification disciplines.
• Maintain the capacity to work extended operational hours and weekend shifts to satisfy critical project delivery deadlines.
• Absolutely meet ITAR compliance requirements by being a U.S. citizen, lawful permanent resident, refugee, or asylee.
• Exhibit strong analytical capabilities with the ability to deconstruct complex system problems into manageable technical components.
• Develop effective communication skills to translate technical issues for stakeholders with varying engineering backgrounds.
• Cultivate resilience when managing competing priorities in a fast-paced aerospace technology development environment.
• Commit to adherence of strict documentation standards and procedural compliance within regulated engineering workflows.

Nice to have

• Earn a Master degree in a relevant technical discipline such as electrical engineering or computer engineering.
• Achieve proficiency with Cadence Virtuoso design environment and Spectre simulation platforms.
• Demonstrate advanced scripting capabilities in Python, Tcl, shell scripting languages, Perl, or SKILL programming.
• Accumulate hands-on experience with diverse foundry PDKs, rule decks, and semiconductor model files.
• Develop familiarity with HPC job schedulers including Slurm workload manager or Platform LSF batch systems.
• Express interest in applying artificial intelligence and large language model technologies to enhance EDA diagnostic processes.
• Show curiosity about machine learning applications for automated flow optimization and pattern recognition in design data.

Practical notes

• Compensation is structured at Level 1 ranging from $125,000 to $150,000 annually or Level 2 compensation from $145,000 to $175,000 based on demonstrated experience and technical qualifications.
• Comprehensive benefits package includes company equity participation through stock awards, performance-based cash awards, 401(k) retirement savings plan with company match, and extensive medical coverage including dental and vision insurance.
• Eligible candidates may access paid parental leave policies and receive three weeks of annual vacation time in addition to more than 10 recognized company holidays.
• Transportation support includes company shuttle services operating from selected locations within the Seattle metropolitan area to the Redmond office campus.
• This position requires physical presence at the designated Redmond, Washington office location.
• All employment decisions are made without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, or disability.