Sr. Full Chip Physical Verification Engineer

About the role

SpaceX is building advanced silicon for global satellite and ground infrastructure to expand the Starlink network. You will join a cross-disciplinary team to manage full-chip physical verification and ensure tapeout readiness for next-generation hardware. In this capacity, you will own the end-to-end signoff of critical silicon components, ensuring that design intent is preserved across multiple abstraction layers. You will act as the primary authority for physical correctness, resolving block-level issues that could delay tapeout. Your work will directly influence the reliability and performance of satellite and ground infrastructure chips shipped from Irvine. You will partner with design, integration, and test teams to validate that each hardware revision meets stringent quality and schedule targets. This role requires a disciplined approach to verification, proactive risk management, and alignment with strict aerospace and defense compliance standards.

Key facts

What you'll do

• Execute full-chip signoff for DRC, LVS, ESD, PERC, and antenna using industry-standard tools to certify design integrity.
• Create and improve physical verification workflows for advanced node SoCs, focusing on scalability, automation, and early error detection.
• Translate foundry Design Rule Manuals into functional flow updates, ensuring rule decks are correctly interpreted and implemented.
• Troubleshoot and fix complex hierarchical DRC and LVS violations, navigating large topologies and multi-level hierarchies with precision.
• Validate ESD protection strategies and compliance for CDM and HBM, confirming that robustness targets are consistently met.
• Manage tapeout coordination between block, top-level, and Hard IP teams, synchronizing schedules, data, and signoff artifacts.
• Communicate with foundries to resolve rule deck questions and waiver requests, documenting decisions and impacts for auditability.
• Integrate AI agents to automate signoff reporting, violation triage, and rule deck validation, enhancing throughput and consistency.
• Develop custom scripts and verification utilities to accelerate regression analysis and root cause investigation.
• Track and report verification metrics, including defect density, closure rate, and risk exposure for executive and engineering reviews.
• Mentor junior engineers on best practices, tool usage, and problem-solving techniques to elevate team capability.
• Collaborate with architecture and layout professionals to resolve early-stage issues before they propagate to later phases.
• Maintain up-to-date knowledge of emerging node technologies, I/O standards, and packaging approaches relevant to satellite applications.
• Ensure all physical verification activities are traceable, auditable, and aligned with project milestones and quality gates.

Requirements

• Bachelor degree in Computer Science, Computer Engineering, or Electrical Engineering.
• 5+ years of industry experience in ASIC or physical design flow development.
• Availability to work weekends and extended hours to hit project deadlines.
• Must meet ITAR requirements (U.S. citizen, lawful permanent resident, refugee, or asylee).
• Proven ability to perform full-chip signoff in at least one advanced node technology.
• Demonstrated experience with DRC, LVS, ESD, PERC, and antenna rule decks and their associated tool chains.
• Strong understanding of foundry constraints, process corners, and how they affect physical verification outcomes.
• Experience managing large designs that exceed 10M gates and operate at or above 1GHz frequency.
• Familiarity with SoC top-level methodologies, including floorplanning, I/O planning, power grid generation, and RDL considerations.
• Capability to script in at least one high-level language such as Python, TCL, Perl, bash, csh, or Makefile to automate verification tasks.
• Track record of working effectively in regulated environments where compliance, documentation, and traceability are critical.
• Willingness to engage with external partners, including foundries, to resolve technical and contractual constraints.
• Commitment to maintaining confidentiality and adhering to strict export control and security protocols.
• Ability to thrive in a fast-paced, deadline-driven environment with frequent context switching and evolving requirements.

Nice to have

• Expertise in SoC top-level physical design, including floor-planning, I/O, bump and RDL planning, and power grid generation.
• Experience with IP integration for SerDes, DDR, analog IPs, and memories within complex SoCs.
• Hands-on proficiency with Pegasus, ICV, or Calibre for signoff and debug activities.
• Background in advanced nodes of 4nm or smaller, with an understanding of how scaling impacts verification challenges.
• Experience with large SoCs exceeding 10M gates and 1GHz frequency, including strategies for managing timing, power, and electromigration.
• Strong scripting abilities in Python, TCL, Perl, bash, csh, or Makefile to build robust verification infrastructure.
• Prior exposure to AI-assisted verification flows or tooling for automating signoff reporting and rule deck validation.
• Familiarity with aerospace, defense, or telecom standards that influence physical verification requirements.
• Experience contributing to open-source or internal verification frameworks that improve team efficiency.
• Willingness to participate in on-call rotations to address critical tapeout issues as they arise.

Practical notes

Compensation includes base salary, potential long-term incentives (stock/options/cash), discretionary bonuses, and the Employee Stock Purchase Plan. Benefits include medical, dental, vision, 401(k), life insurance, disability insurance, paid parental leave, 3 weeks of vacation, 10+ holidays, and 5 days of sick leave. SpaceX is an Equal Opportunity Employer.

About the company

Based in Starbase, Texas, a company pursues work in spaceflight, telecom, and artificial intelligence. A unit handles rocket launches, leading yearly orbital counts beyond other national and commercial teams. Another unit runs Starlink, a satellite communications firm. A third area, through SpaceXAI, advances Grok and AI integration with X, while managing data center operations. Roles often cross these paths. Candidates with engineering, software, or operations backgrounds may find chances to join projects that span launch, connectivity, and machine learning efforts in this Texas-based enterprise.