Principal ASIC Design Engineer

About the role

Join the Starshield team to develop advanced hardware for national security missions. You will build next-generation FPGAs and ASICs for space and ground infrastructure, focusing on rapid iteration to move from design to operational deployment. This role places you at the intersection of secure communications and cutting-edge semiconductor design, where your work will directly influence mission-critical capabilities. You will own the full design lifecycle from architectural exploration through tapeout and silicon validation in a fast-paced environment. The position demands a high degree of ownership, requiring you to solve ambiguous technical problems with minimal guidance. You will interface closely with systems engineers, verification experts, and physical implementation teams to ensure robust and manufacturable solutions. Success in this role is defined by your ability to deliver timing-clean, high-performance hardware on schedule against strict operational requirements.

Key facts

What you'll do

• Design digital ASICs and FPGAs for Starshield projects, translating complex system requirements into high-integrity hardware solutions.
• Evaluate architectural trade-offs to define specifications and partition hardware and software functions with RFIC and modem/DSP engineers, ensuring optimal performance and power efficiency.
• Develop micro-architectures and implement RTL in Verilog or System Verilog, writing clean, synthesizable, and testable code.
• Deliver synthesis and timing-clean designs while managing top-level integration, block-level signoff, and cross-module interfacing.
• Collaborate with verification teams to ensure full design coverage, working with constrained-random and directed test strategies to validate functionality.
• Provide timing constraints and support physical implementation, including formality checks, clock and data optimization, and signoff activities with the EDA group.
• Conduct silicon bring-up and validation, including the creation of automated test lab equipment to accelerate debug and characterization.
• Partner with firmware and systems engineers to define bootflows, memory maps, and register interfaces that enable seamless hardware/software co-design.
• Mentor junior engineers on best practices for ASIC development, code reviews, and verification methodologies to elevate team capability.
• Drive the creation and maintenance of reusable IP blocks, ensuring compliance with security, reliability, and performance standards for defense applications.
• Analyze failure modes and root-cause issues in silicon, updating test plans and design fixes to achieve yield and reliability targets.
• Contribute to the definition of product requirements and technical roadmaps, providing architecture input that shapes future generations of secure space hardware.
• Maintain strict documentation of design decisions, verification plans, and validation results to support audits, certifications, and regulatory compliance.
• Operate within the constraints of ITAR-controlled programs, ensuring that all design artifacts and technical discussions adhere to export control and security protocols.

Requirements

• Bachelor degree in computer science, computer engineering, or electrical engineering.
• 8+ years of experience in ASIC/FPGA development or RTL implementation, with a proven track record of delivering tapeout projects.
• Must be a U.S. citizen, lawful permanent resident, refugee, or asylee to comply with ITAR regulations.
• Demonstrated ability to manage multiple design tasks simultaneously while meeting aggressive deadlines in a high-security environment.
• Strong understanding of digital logic design, finite state machines, and synchronous methodologies at the ASIC block level.
• Experience with at least one advanced HDL, such as Verilog or System Verilog, including writing testbenches and self-checking testcases.
• Knowledge of synthesis and timing analysis flows using industry-standard tools and constraints methodologies.
• Familiarity with secure development practices, including code reviews, version control, and traceability of requirements to implementation.
• Ability to work effectively in a cleared environment, adhering to strict documentation and change control procedures.
• Willingness to accept long hours, weekend work during critical milestones, and travel for off-site testing and integration activities.

Nice to have

• Experience with multicore CPU subsystems and embedded processors.
• Proficiency in high-speed, low-power design techniques.
• Knowledge of standard bus protocols like AXI or AHB.
• Experience with clock domain crossings and power optimization.
• Scripting skills in Python or TCL.
• Familiarity with EDA tools including HDL simulators like VCS, Questa, or IES, linting tools like Spyglass, and FPGA tools like Altera Quartus II or Xilinx Vivado.

Practical notes

• Salary range: $200,000 to $285,000 per year.
• Active TS-SCI clearance holders receive a 10% differential up to $20,000 annually upon briefing into classified programs.
• Compensation includes long-term incentives such as stock options or cash awards, discretionary bonuses, and an Employee Stock Purchase Plan.
• Benefits include medical, dental, vision, 401(k), life insurance, disability insurance, and paid parental leave.
• Accrue 3 weeks of paid vacation plus 10+ holidays and sick leave.
• Expect long hours, weekend work during milestones, and travel for off-site testing.
• Active TS-SCI clearance holders are subject to pre-employment and random drug and alcohol testing.