HBM Logic Architect

About the role

The role manages customer-driven solutions for base-die challenges in HBM and 3D-stacked DRAM. It directs the creation of a focused US architecture team to handle these engagements. Efforts center on advancing customized memory architectures to sustain market leadership. You will define and own the strategic technical direction for HBM base-die solutions in the US market, ensuring alignment with both customer needs and corporate vision. This position requires you to translate abstract customer requirements into concrete architectural frameworks and implementation plans. You will act as the primary technical authority, guiding complex engagements from initial concept through to final execution. Success in this role depends on your ability to synthesize intricate customer problems into coherent, actionable architecture strategies. You will be responsible for building the credibility and trust necessary to lead cross-functional initiatives with key United States stakeholders.

Key facts

What you'll do

Digital IP for ASIC and SoC products is defined, designed, and validated to satisfy customer specifications for HBM and 3D-stacked memory solutions. RTL design and implementation are performed following approved specifications to achieve intended functionality within strict memory system constraints. Cross-functional collaboration defines IP functionality, behavior, and architecture for HBM and DRAM solutions, interfacing closely with design, verification, and physical teams. Digital IP requirements are reviewed, and architecture options are evaluated against power, performance, and area targets to meet competitive market demands. Architecture decisions for digital IP implementation in memory systems are determined or contributed to, influencing methodologies and design standards. RTL designs are developed and verified using established methodologies to guarantee correctness, robustness, and functional coverage across all operational modes. Design guidance is supplied to support physical design implementation and streamline tapeout, ensuring signal integrity and manufacturability are addressed early. System-level co-optimization is driven to enhance overall memory subsystem performance beyond standalone components, considering the entire base-die ecosystem. Deep technical partnerships with U.S.-based customers are built to align solutions with market demands and emerging application scenarios. Competitiveness is improved through close engagement with United States customers by providing tailored architectural solutions and strategic technical leadership.

Requirements

A Bachelor's degree or higher in Electrical Engineering or a related discipline (Master's preferred) is mandatory for this position. At least 5 years of relevant experience in semiconductor, ASIC/SoC, digital IP, memory, or PHY design is required to be considered. Demonstrated capability in high-speed digital PHY or high-speed IP design and analysis for demanding applications is necessary for success. Proven experience in DRAM memory controller design and analysis to meet complex protocol requirements is essential. Knowledge of DRAM DFT and DFD architecture, design, or analysis to enable testability and yield is required. Skills in PHY/TSV bit macro design, TSV PHY hard macro design, or 3D PHY design for advanced packaging scenarios are required. Preferred experience in PPA (Power, Performance, Area) optimization to balance trade-offs across performance metrics is expected. Candidates must be able to clearly articulate technical concepts in writing and verbal communication to diverse audiences. The ability to manage multiple priorities and deadlines in a fast-paced, deadline-driven environment is a hard requirement.

Practical notes

Work model is fully onsite at the San Jose location. This role involves building and leading a team with direct, real-time support for US customers. Typical interview steps usually combine a screening conversation with one or more interview rounds. Candidates can expect questions about their experience, a scenario or case, and a chance to ask their own questions. Preparation and specific examples from past work carry the most weight. Whatever the role, preparation is visible. Reviewing the company's product, the job description, and your own past work before the conversation is the strongest step.

Good to know

The role focuses on digital architecture and verification for high-bandwidth memory solutions. Common tools in this field include logic synthesis, static timing analysis, and hardware verification platforms. Design for testability and yield optimization are important considerations for memory IP. Cross-functional collaboration is central to defining and delivering competitive memory architectures. Senior specialists often drive system-level optimization across memory controllers and interfaces.