Senior Staff Engineer, SoC Architecture - Memory Subsystem and Interconnect

About the role

This role defines high-performance SoC architecture for Galaxy devices. You will evaluate memory hierarchy microarchitectural features through performance modeling and simulation to support their inclusion in future generations of SoC designs. You will define subsystem architecture proposals for existing and new markets, aligning them precisely with product goals and delivering them to product teams. You will evaluate the benefits of architecture proposals in collaboration with SoC architects and communicate results clearly across hardware, software, architecture, and leadership audiences. You will extend microarchitectural proposals across the SOC, drivers, OS, and system through detailed documentation to ensure cross-team cohesion. This position requires balancing memory systems and computer architecture background to manage bandwidth, latency, performance, power, and SoC area tradeoffs effectively. You will leverage deep expertise in memory controller architecture, memory scheduling, prioritization, and QoS to guide complex design decisions. The role operates within a research lab that drives flagship product features and interfaces continuously with hardware, software, and leadership stakeholders.

Key facts

Location: USA

Engagement: Office-based

Team: SoC Architecture Lab

Years: 12+ total experience, 9+ specific experience

Degree: BSc, Masters, or PhD required

The posting states a pay range of $197800 to $296600.

What you'll do

Evaluate memory hierarchy microarchitectural features through performance modeling and simulation to justify inclusion in next-generation SoC designs.

Define subsystem architecture proposals for current and emerging markets, aligning them with ambitious product goals and delivering them to product teams.

Collaborate with SoC architects to evaluate benefits of proposed architectures and communicate outcomes to hardware, software, architecture, and leadership stakeholders.

Extend microarchitectural proposals across the System on a Chip, drivers, operating system, and system software through detailed and precise documentation.

Balance memory systems and computer architecture background to optimize bandwidth, latency, performance, power, and SoC area for competitive products.

Apply deep understanding of memory controller architecture, memory scheduling mechanisms, prioritization strategies, and quality of service policies in design decisions.

Analyze ARM bus infrastructure details including ACE, AXI, and AHB to ensure robust and scalable interconnect implementations.

Utilize JEDEC standards such as LPDDR, DDR, and HBM to analyze requirements and drive actionable recommendations for memory subsystem designs.

Work within a research lab environment that defines flagship product features and coordinates closely with hardware, software, and executive stakeholders.

Guide cross-functional teams by translating complex memory subsystem and interconnect concepts into clear directions and actionable tasks.

Requirements

A BSc, Masters, or PhD in Computer Science/Engineering or an equivalent combination is mandatory.

Direct experience exceeding 9 years in Fabric, System Cache, or DRAM controller architecture or microarchitecture is required.

Memory controller architecture, memory scheduling, prioritization, and QoS must be understood in detail.

ARM bus infrastructure, including ACE, AXI, and AHB, must be known in detail.

JEDEC standards such as LPDDR, DDR, or HBM must be understood, and the ability to analyze such standards and drive recommendations is required.

Memory systems and computer architecture background is used to balance bandwidth, latency, performance, power, and SoC area.

This role requires office presence at the listed address in Mountain View, California.

Typical interview steps include a recruiter screen, one or two technical rounds, coding problems, discussion of past projects, and system design questions.

Final rounds typically cover team fit and provide candidates an opportunity to ask questions about the role and expectations.

Interviewers focus on how candidates break down unfamiliar problems, emphasizing structured thinking rather than only reaching the answer.

Nice to have

Specialists model and explore system-level architectures for mobile SoCs, focusing on memory hierarchy and interconnect.

Work spans modeling, specification, and cross-team collaboration using common architecture exploration platforms and simulators.

Practical notes

This role requires office presence at 665 Clyde Avenue, Mountain View, CA, USA.

Typical interview steps include a recruiter screen followed by technical rounds, coding problems, past project discussions, and system design questions.

Final rounds cover team fit and provide an opportunity for candidates to ask questions.

Candidates should prepare by practicing a few problems aloud and reviewing their own past projects.

Career growth and useful questions

Engineering careers usually progress from individual contributor to senior, staff, and principal levels. Some engineers move into management and lead teams of five to twenty people, while others remain on the technical track. Growth follows demonstrated impact, not tenure alone, and a typical engineering ladder has clear levels with defined expectations for scope, quality, and mentorship. Moving up usually requires owning outcomes end to end rather than completing assigned tickets. During interviews, you may ask what a typical week looks like, how work is assigned, what tools the team uses, and how feedback is provided. It is also reasonable to ask how the role has changed recently and what the team wishes it had known when joining. Questions about the manager's priorities are especially valued by the interview team.