HPC SoC Timing Design Engineer/Leader

About the role

You will own the clock strategy for demanding automotive chips that integrate CPU, cache, memory, high-speed interfaces, AI, video, functional safety, and security. This position requires you to shape schedules and define solutions within tight development windows while navigating the pressure of rising performance demands and cost competitiveness. You will drive novel timing fixes across multiple design teams, balancing risk, coverage, and signoff for complex silicon in a distributed environment. Clear communication in English is essential as you collaborate with centers in Vietnam and India to ensure alignment on critical timing objectives. The role demands innovative thinking to develop products with short turnaround times under increasingly complex market conditions. You will establish hierarchical constraints and define setup and hold goals for critical paths early in the design cycle to prevent downstream issues. Leading cross-site verification is a primary duty, ensuring consistent timing reports and methodologies across global locations. This position requires you to guide junior staff, coach review practices, and ensure documentation for timing closure accountability and continuous improvement.

Key facts

What you will do

You will establish hierarchical constraints and define setup and hold goals for critical paths early in the design cycle to ensure robust timing closure from the outset. Leading cross-site verification is a primary duty, involving the alignment of scripts, methodologies, and metrics between design centers in Japan, Vietnam, and India to ensure consistent timing reports and reduce ambiguity. This ensures consistent timing reports across locations, enabling efficient decision-making and reducing rework. Driving gate based signoff requires close coordination with labs to validate voltage corners, process shifts, and environmental conditions to confirm that the design meets specifications in real-world scenarios. Planning floor arrangements is part of the role, including the placement of macros and standard cells to meet timing, congestion, and power objectives while avoiding physical bottlenecks. The goal is to meet timing and congestion objectives through careful analysis and iteration in collaboration with layout and physical verification teams. Reviewing block interactions is necessary to resolve cross-domain noise, clock domain crossing issues, and routing congestion that can significantly impact arrival times and signal integrity. You will partner with analysis groups to model wire loads and estimate parasitics for late stages, ensuring that timing predictions are accurate and signoff-ready. Guiding junior staff is a key leadership component, where you will coach review practices, conduct design critiques, and ensure documentation for timing closure accountability across the project lifecycle. Tracking timing trends across multiple chips allows for methodology refinement, enabling you to identify recurring issues and implement preventive actions. This work aims to accelerate iterations and reduce iteration depth by improving automation, constraints, and signoff confidence. You will collaborate with functional safety and security teams to ensure that timing constraints reflect the correct operational modes and fault scenarios. Engaging with verification groups, you will define timing exceptions, waiver strategies, and coverage signoff criteria to ensure comprehensive validation. You will support the integration of HPC and automotive features, ensuring that high-speed interfaces, AI engines, and memory subsystems meet performance targets. You will participate in risk assessment and mitigation planning, identifying potential timing bottlenecks and proposing actionable solutions early in the project. This role requires you to stay current with advances in semiconductor nodes, timing analysis methodologies, and EDA tool enhancements to maintain a competitive edge.

Requirements

You must hold three to five years of digital design experience within the semiconductor timing domain to ensure familiarity with real-world timing challenges. Demonstrated hands-on skill with static timing analysis and its associated toolchains is mandatory for effective timing diagnosis and optimization. Experience crafting constraints using related scripting for synthesis and signoff is required to automate and standardize timing flows. You must show comfort engaging with teams in Vietnam and India, reflecting the global and distributed nature of the work environment. The working language for all collaboration is English, and you must be able to communicate clearly and professionally in written and verbal forms. A strong understanding of automotive and HPC chip architectures is essential to align timing strategies with system-level requirements. You must be proficient in using Cadence, Synopsys, and Siemens toolsets to perform timing analysis, optimization, and signoff. Experience with MATLAB, Perforce, Git, and Docker is required to support automation, version control, and containerized workflows. You must be able to work independently and as part of a cross-functional team in a fast-paced, deadline-driven environment. Strong problem-solving skills and a methodical approach to debugging timing issues are essential for success in this role.

Nice to have

Demonstrated experience with HPC or automotive chips is highly valued, as it provides context for timing closure in safety- and performance-critical applications. Familiarity with ISO standards is also considered an asset for this role, particularly related to functional safety and quality management in automotive electronics.

Practical notes

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