Senior Compiler Engineer

About the role

You will architect and implement compiler transformations that maximize the energy efficiency of our novel dataflow processor while preserving a consistent programming model for AI and ML workloads. This role places you at the intersection of hardware and software, where your work will directly enable pervasive, perpetual intelligence on edge devices powered by a simple AA battery. You will own the critical path between high-level ML frameworks and the silicon, ensuring that the theoretical efficiency of the hardware is realized in real-world applications. You will investigate and resolve deep optimization challenges, turning complex hardware constraints into robust features for downstream developers. Your contributions will be visible across the stack, influencing both the low-level execution engine and the high-level tools used by our application teams. You will partner with interdisciplinary experts to validate that compiler outputs meet stringent power, timing, and accuracy targets for next-generation IoT deployments. This position is ideal for a hands-on engineer who thrives on solving hard problems that have a direct impact on the future of computing.

Key facts

What you'll do

Design and implement compiler passes that optimize for the unique dataflow instruction set architecture of Efficient's processor, focusing on throughput and energy metrics.

Perform memory access analysis and ordering transformations to minimize data movement and respect strict hardware timing and power constraints.

Develop tools for placement and routing of computational workloads onto the heterogeneous fabric of the target device.

Create visualization and introspection capabilities that allow programmers to understand and debug complex compiler behavior.

Build and maintain unit and integration test suites that expose functional defects and performance regressions in the compilation pipeline.

Collaborate with machine learning framework maintainers to lower models such as TensorFlow and PyTorch to an efficient executable form.

Debug intricate compiler issues that manifest only under specific hardware configurations or workload patterns.

Partner with the physical design and hardware architecture teams to provide feedback that shapes future iterations of the processor.

Work closely with the application development organization to understand emerging AI/ML use cases and tailor compiler solutions to those demands.

Champion the adoption of the compiler stack within the developer community by producing clear documentation and actionable tooling.

Investigate novel compilation techniques from academic research and evaluate their applicability to our energy-efficient platform.

Ensure that all compiler-generated code adheres to the security and reliability standards required for pervasive edge intelligence.

Integrate profiling feedback to drive iterative improvements to the compiler's optimization heuristics.

Act as a technical leader in defining best practices for efficient model deployment on battery-powered devices.

Requirements

Possess 6 or more years of professional experience using C++ in a production software environment.

Hold a Bachelor's or Master's degree in Computer Science or a closely related technical field.

Demonstrate familiarity with established compiler frameworks such as GCC, LLVM, and MLIR.

Show a deep understanding of computer architecture concepts, including instruction-level parallelism, memory hierarchies, and power-aware design.

Have hands-on experience with industry-standard development and debugging tools, including GDB, to diagnose complex issues.

Exhibit strong attention to detail, a rigorous work ethic, and the ability to successfully manage multiple concurrent projects.

Communicate technical ideas clearly and effectively to both technical and non-technical stakeholders.

Solve difficult problems systematically, using evidence and experimentation to guide your implementation decisions.

Nice to have

Bring prior experience with FPGA compilation flows or physical synthesis placement and routing algorithms.

Show background with hardware description languages such as Verilog, SystemVerilog, or VHDL.

Possess an advanced knowledge of computer microarchitecture and low-level optimization strategies.

Practical notes

This is a full-time position.

Compensation details are provided in the key facts section.

No specific travel, visa, or application deadline information is provided in the source text.