Senior Staff Power Performance Architect Accelerator Design

About the role

You will own the end-to-end power and performance validation of AI accelerator blocks from RTL through physical signoff. You will collaborate closely with frontend architects and DV engineers to profile workload activity windows and turn analysis into actionable power optimizations. You will architect a scalable power estimation flow for AI workloads using system configuration and die-level metrics as inputs. You will drive the integration of performance monitor requirements and boost features with frontend and backend teams to influence die modifications. You will leverage your expertise in micro-architecture and RTL to guide synthesis and physical implementation decisions that meet power targets. You will implement performance enabling and power monitoring functions while participating in silicon bring-up and validation. You will build and maintain scripts that automate power analysis across the design team to improve execution productivity.

Key facts

What you'll do

• Conduct pre-silicon power estimation for design blocks covering both RTL power and physical design power.
• Partner with front-end and DV engineers to identify power activity windows and ensure optimization feedback is implemented.
• Construct an architectural power estimation tool for AI workloads computing power from system configuration and die-level metrics.
• Work with frontend architects and backend design to compile performance monitor availability, system requirements, and usage.
• Feed analysis results to the frontend team to integrate feedback into the design and improve hardware capabilities.
• Perform micro-architecture and RTL design, synthesis, logic and physical power performance verification using leading-edge CAD tools and semiconductor process technologies.
• Design and implement performance enabling and power saving or monitoring functions that enable efficient design, test, and debug.
• Participate in silicon bring-up and validation to resolve power and performance issues early.
• Build script utilities in TCL and Python to automate workflows and improve design execution productivity across the team.
• Traverse and context switch between RTL, physical design, and automation with comfort and speed.
• Contribute strong engineering judgment to make design calls and prefer action over advice while iterating at a fast cadence.
• Drive adoption of power estimation flows by deploying usage across the design team and ensuring consistent results.

Requirements

• Hold a Master's degree in electrical engineering, Computer Engineering, or Computer Science as a baseline qualification.
• Demonstrate deep understanding of power, performance, micro-architecture, RTL, physical design, and digital system IC design.
• Show familiarity with the complete ASIC design flow from architecture to fabrication and verification.
• Have experience with at least one EDA tool dedicated to power estimation within the design flow.
• Be comfortable moving between RTL, physical design, and automation to meet project deadlines.
• Apply programming skills in TCL and Python to automate analysis, data parsing, and algorithmic thinking.
• Exhibit a strong willingness to contribute and be self-motivated in a fast-paced environment.
• Readily pick up new design activities, modify existing flows, and iterate quickly using engineering judgment.
• Understand performance metrics and their relationship to hardware behavior and system configuration.
• Value direct communication, humility, and respect as core traits that support collaboration.
• Thrive in an inclusive culture where differing perspectives lead to better solutions.
• Be driven by execution and passionate about tackling challenges in AI accelerator design.

Nice to have

Additional exposure to system or IC design points such as TDP, PMAX, EDP, Peak, and Average is valuable. Familiarity with dynamic frequency and voltage scaling including DFS, DVFS, AFS, and AVFS is valuable. Knowledge of PDN, resonance, Z(f), and droop analysis is valuable.

Practical notes

Hybrid schedule with working onsite at our Santa Clara, Ca headquarters 3-5 days per week. This role requires presence during key project milestones and tapeout activities. Employment is at-will in compliance with local regulations. d-Matrix is an equal opportunity employer and does not accept resumes from external agencies.