Principal Software Engineer in Test

About the role

This senior individual contributor position spearheads the Software Qualification group responsible for validating the D Matrix AI compute engine. The role demands ownership of technical testing strategies and the mentorship of junior engineers while constructing robust infrastructure to verify the complete stack ranging from firmware up through machine learning workloads. You will act as a technical anchor ensuring the reliability of a novel digital in-memory compute platform designed for transformer inference. Success requires bridging deep hardware knowledge with modern software engineering practices to de-risk silicon bring-up and production deployment.

Key facts

What you'll do

• Mentor junior staff on advanced test planning methodologies, automation architecture design, and systematic debugging techniques to elevate overall team capability.
• Partner closely with product management and systems engineering groups to define and implement comprehensive coverage strategies for newly developed features and silicon revisions.
• Spearhead root cause analysis investigations for complex test failures, orchestrating cross-functional resolution workflows to ensure timely closure.
• Architect, develop, and maintain highly scalable Python-based test suites leveraging the Pytest framework for maximum maintainability and parallel execution.
• Embed validation workflows deeply into continuous integration and delivery pipelines utilizing Jenkins and GitLab to enforce quality gates on every commit.
• Execute rigorous validation of low-level hardware components including FPGA bitstreams, bootloader sequences, and host runtime driver interactions.
• Verify system-level integration across heterogeneous compute environments involving host CPUs, GPUs, and the proprietary D Matrix AI accelerators.
• Translate technical quality metrics and risk assessments into clear, actionable insights for both engineering leadership and non-technical stakeholders.
• Develop specialized test harnesses and simulation models to exercise firmware-hardware interfaces prior to silicon availability.
• Define and enforce coding standards, review processes, and documentation practices for all test automation assets.
• Drive the adoption of static analysis, code coverage tooling, and mutation testing to quantitatively improve test effectiveness.
• Collaborate with architecture teams to inject testability hooks (DFT/BIST) into future hardware revisions based on validation gaps observed in current generation.

Requirements

• Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a closely related technical discipline.
• Minimum of 10 years of progressive industry experience in software or hardware validation roles.
• At least 8 years of professional software development experience demonstrating mastery of data structures, algorithms, and object-oriented design patterns.
• Minimum 8 years of hands-on experience testing lower-layer software stacks encompassing FPGAs, bootloaders, kernel modules, and host device drivers.
• Five or more years of direct firmware design, implementation, and low-level troubleshooting experience on embedded platforms.
• Three or more years of practical experience with embedded system architectures and high-speed I/O technologies, specifically PCIe Gen4/Gen5 protocols.
• Expert-level proficiency in Python for developing production-grade, maintainable test frameworks and infrastructure tooling.
• Proven track record of debugging intricate issues that span the hardware-software boundary, utilizing tools such as logic analyzers, JTAG debuggers, and protocol analyzers.
• Demonstrated ability to lead technical initiatives autonomously and influence cross-functional teams without direct managerial authority.

Nice to have

• Direct experience with machine learning frameworks such as PyTorch or TensorFlow and deep understanding of accelerator architecture dataflows.
• Familiarity with Large Language Model architectures, inference optimization techniques (quantization, sparsity), and serving stacks.
• Prior tenure in a Principal, Staff, or Lead-level Quality Assurance or Test Engineering role within a semiconductor or systems company.
• Experience with hardware emulation environments (Palladium, Zebu) or RTL simulation for pre-silicon validation.
• Knowledge of container orchestration (Kubernetes) and bare-metal provisioning tools for lab automation at scale.
• Background in safety-critical or automotive qualification standards (ISO 26262) applied to AI hardware.

Skills & tools

• Python, Pytest, Jenkins, GitLab CI/CD, PCIe, FPGA, Firmware Development, Embedded Linux, C/C++, ML Accelerators, Transformer Architecture, JTAG, Logic Analyzers, Protocol Analyzers, Git, Linux Kernel Internals, CI/CD Pipeline Design, Test Architecture.

Practical notes

• D Matrix does not accept resumes or candidate submissions from external recruitment agencies; all applicants must apply directly through official company career channels.
• The hybrid work model requires regular on-site presence at the Santa Clara headquarters for lab access, hardware bring-up, and cross-team collaboration.
• Visa sponsorship eligibility is assessed on a case-by-case basis depending on role requirements and candidate qualifications.
• The compensation range reflects base salary only; total compensation includes a significant equity component and performance-based bonus structure.
• This role involves occasional travel to foundry partners or remote test labs for silicon validation milestones.