Senior Staff PCB Layout Design Engineer

About the role

You will own the physical architecture that connects d-Matrix silicon to high-speed networks, defining how power and signals coexist on complex boards. In this role, you will lead the layout of intricate AI accelerator systems that demand flawless signal integrity for 112G and 224G SerDes channels. You will act as the custodian of our design methodology, establishing the rules and automation that ensure consistency across every project phase. Your work will directly shape the reliability and performance of our next-generation hardware platforms. You will partner closely with cross-functional teams to translate system requirements into robust physical implementations. This position requires a hands-on leader who drives execution while mentoring others on best practices. Together, you will build the infrastructure that supports the endless possibilities of AI compute.

Key facts

What you'll do

• Assume full ownership of system layout for high-complexity AI accelerator cards and massive baseboards in server form factors.
• Architect and manage the Constraint Manager hierarchy in Cadence Allegro, establishing the source of truth for high-speed rules and electrical constraints.
• Drive productivity by developing automation scripts in SKILL, Python, or TCL to streamline layout tasks, DRC checks, and report generation.
• Execute layout for ultra-high-speed interfaces such as PCIe Gen5 and Gen6, CXL, and custom die-to-die interconnects.
• Collaborate with power engineering teams to implement advanced PDN strategies, including multi-phase VRM layouts and optimized decoupling capacitor placement.
• Define PCB stack-ups by selecting advanced low-loss materials like Megtron 7 or 8 and managing hybrid build-up strategies.
• Interface directly with PCB fabricators and contract manufacturers to enforce DFM, DFT, and DFA requirements for high-yield production.
• Lead the implementation of back-drilling, via-in-pad, and skip-via techniques to meet stringent high-speed signal requirements.
• Standardize footprint and padstack creation while establishing library management systems to ensure design integrity.
• Integrate PLM or PDM workflows to control layout releases and manage ECO processes efficiently.
• Apply warpage mitigation strategies for large-form-factor ASICs and multi-chip modules to prevent assembly defects.
• Ensure successful routing of 112G SerDes and complex DDR5/HBM interfaces while maintaining timing and impedance targets.
• Perform design audits using automated scripts to verify constraints, spacing, and manufacturing rules before tapeout.
• Support qualification and validation activities that prove the robustness of the physical design in real-world conditions.

Requirements

• Hold a Bachelor of Science in Electrical or Electronic Engineering or possess equivalent practical experience.
• Bring a minimum of 12 years of hands-on experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators.
• Demonstrate expert-level mastery of Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matching.
• Show proven ability to write and deploy SKILL scripts or use Allegro APIs for automating design audits and layout routines.
• Exhibit deep knowledge of high-speed routing techniques, including back-drilling, via-in-pad, and skip-vias.
• Have substantial experience with HDI (High-Density Interconnect) and ELIC (Every Layer Interconnect) methodologies.
• Maintain a proven track record of routing 112G SerDes and complex DDR5 or HBM interfaces successfully.
• Understand power delivery networks and their interaction with signal integrity in high-TDP designs.
• Communicate effectively with external vendors to resolve manufacturing and assembly challenges.
• Adhere strictly to d-Matrix standards for documentation, version control, and design reviews.

Nice to have

• Experience establishing library management systems and standardized footprint and padstack creation processes.
• Familiarity with PLM or PDM integration for managing layout releases and ECO workflows.
• Knowledge of PCB warpage mitigation strategies for large-form-factor ASICs and multi-chip modules.

Practical notes

This role is based in Santa Clara, California, and follows a hybrid or on-site schedule as defined by d-Matrix policies. There may be limited travel required to support manufacturing or customer engagements. Employment is contingent on eligibility to work in the United States, and d-Matrix will sponsor qualified candidates when authorized. This job description is intended to convey the general nature and level of work performed and does not limit the flexibility or autonomy expected of the role.