Senior Staff Hardware Qualification Engineer

About the role

You are the final gatekeeper of quality and reliability for our next-generation AI compute platforms, owning the end-to-end qualification of hardware that powers generative AI at scale. This high-impact, technical leadership role demands ownership of strategies that ensure ASIC substrates and rack-scale systems withstand the unrelenting demands of 24/7 data center operations. You will bridge the gap between design and mass production, ensuring that cutting edge does not equate to fragile under real-world conditions. Working at the intersection of design, validation, and manufacturing, you will define what it means for a d-Matrix product to be truly production-ready. You will partner with cross-functional teams to translate reliability goals into executable test plans and drive them to completion. Your work will directly influence product stability, customer trust, and the long-term reputation of our Digital In-Memory Computing (DIMC) architecture. Ready to come find your playground where theory meets silicon and systems. Together, we can help shape the endless possibilities of AI through rigorous, innovative qualification.

Key facts

What you'll do

Define and execute comprehensive hardware qualification plans covering EVT, DVT, and PVT stages for complex AI accelerator systems, including PCIe cards, OAM modules, and chassis systems.

Lead the implementation and execution of Highly Accelerated Life Testing (HALT) and Highly Accelerated Stress Screening (HASS), thermal cycling, humidity, and vibration testing to uncover marginalities in high-power ASIC designs.

Provide senior-level oversight for signal and power integrity validation, focusing on high-speed SerDes interfaces at 112G, 224G, and PCIe standards, along with LPDDR configurations and complex PDN transient analysis.

Drive failure analysis for system-level issues using advanced tools such as X-ray, CT scan, and SEM/EDX to differentiate between design flaws, manufacturing defects, and material fatigue.

Oversee the qualification of high-bandwidth interconnects, including equivalents of NVLink and UALink, as well as PCIe Gen5 and Gen6 link stability across thermal and electrical conditions.

Partner directly with design, thermal, and firmware teams to correlate qualification data with design changes, thermal solutions, and firmware workarounds for robust outcomes.

Collaborate with contract manufacturers and joint development partners to align on test methodologies, production outgoing quality limits, and screening criteria.

Establish and maintain statistical analysis frameworks using methods such as Weibull analysis, Design of Experiments (DOE), and tools like JMP or Minitab to predict life cycles and failure rates.

Develop and document test procedures, acceptance criteria, and reporting packages that meet industry standards and support rapid decision-making for product launches.

Champion the qualification of air and liquid cooling components, including cold plates and CDU designs, along with leak detection strategies for high-TDP AI systems.

Lead reliability efforts focused on ASIC/Package-level concerns such as electromigration, Thermal Stress Analysis, and via integrity under sustained load.

Automate complex test sequences and data analysis workflows using scripting in Python or test front panels in LabVIEW to improve throughput and repeatability.

Ensure alignment with JEDEC, IPC, and Telcordia standards for hardware reliability, embedding compliance into qualification flows from planning to sign-off.

Act as the technical authority for interconnect reliability, validating NVLink/UALink equivalents and PCIe Gen5/6 signal integrity across corner cases and environmental extremes.

Maintain traceability between qualification results, failure mechanisms, and corrective actions to drive continuous improvement across the product lifecycle.

Support the creation of qualification documentation required for customer engagements, regulatory submissions, and internal audits.

Promote best practices across the organization by mentoring junior engineers and elevating the maturity of the reliability discipline.

Requirements

BS/MS in Electrical Engineering, Mechanical Engineering, or Reliability Engineering is mandatory for this role.

You bring 12 or more years of hands-on experience in hardware qualification or reliability, with a strong focus on high-performance computing, servers, or networking hardware.

You possess mastery of JEDEC, IPC, and Telcordia standards that govern hardware reliability and lifecycle expectations.

You are an expert with high-speed oscilloscopes, logic analyzers, and environmental chambers, using them daily to characterize hardware behavior.

You apply statistical methods such as Weibull analysis, Design of Experiments, and JMP or Minitab to interpret data and forecast product life cycles and failure rates.

You have a proven track record of defining and driving qualification programs for complex hardware in fast-paced development environments.

You communicate technical findings clearly to both engineering teams and executive stakeholders, ensuring alignment on risk and mitigation strategies.

You are comfortable working in a matrixed organization where priorities shift quickly and collaboration across functions is essential.

Nice to have

Hands-on experience qualifying air and liquid cooling components, such as cold plates and CDU designs, for high-TDP AI systems.

Background in ASIC or package-level reliability, including electromigration analysis and Thermal Stress Assessment.

Experience automating test sequences with Python or building test front panels in LabVIEW for complex validation flows.

Practical notes

This role is based in Santa Clara, California, and follows a hybrid work model with significant onsite presence required.

Travel is not expected as part of the core responsibilities.

Visa sponsorship is not available for this position.

Candidates must be authorized to work in the United States without sponsorship.

The hiring process will move quickly, and early submission of materials is encouraged to secure consideration.