Analog Design Engineer, Staff

About the role

This position is centered on the design of analog and mixed-signal integrated circuits that enable AI accelerator and high-speed interconnect solutions. The hired individual will operate within a culture that values direct communication, collaboration, and diverse perspectives to drive execution. Success in this role is defined by the ability to solve problems efficiently and align closely with partners across disciplines. The engineer will own critical design challenges from specification to silicon, ensuring that performance targets are met. They will translate high-level system requirements into robust analog implementations that support next-generation compute infrastructure. This role requires a disciplined approach to verification and validation to ensure that designs are manufacturable and reliable. The position offers the opportunity to contribute to foundational technology that bridges complex hardware systems.

Key facts

What you'll do

System-level analysis defines performance targets for analog and mixed-signal blocks in AI accelerator and die-die serial interface designs.

Low-power performance across process-voltage-temperature corners and six-sigma Monte Carlo yield analysis is optimized through verification environments and test benches.

Guidance for layout implementation at 7 nm and deeper nodes is provided to enable minor adjustments when necessary.

Silicon bring up and bench characterization are supported by automated scripts and test features built for testing and debug.

Circuit behavior is modeled and delivered to backend teams to support verification and integration with digital logic.

Participation in and contribution to standards bodies is encouraged for those who can influence industry direction.

Verification environments are developed and maintained to ensure that analog behavior meets exacting specifications under all conditions.

Collaboration with digital and system engineers ensures that analog modules integrate seamlessly into larger SoC architectures.

Requirements

A completed BS/MS/PhD in Electrical Engineering is preferred, along with 7 or more years of professional experience in high-speed blocks such as phase interpolator, clocking, and PLL designs.

Schematic capture, Spice simulation, and Monte Carlo simulation experience is required for accurate performance validation.

Circuit layout, extraction, and back-annotated simulation experience is required to close design rules and timing.

Channel modeling using Matlab or equivalent tools is required to support system-level integration and signal integrity analysis.

Effective interpersonal and teamwork skills are required for productive collaboration across distributed teams.

Proficiency working with cross-functional and cross-site teams is required to coordinate dependencies and deliverables.

Excellent communication skills are required to clearly convey design intent, analysis, and trade-offs to both technical and non-technical audiences.

Strong analysis and problem-solving skills are required to address complex design challenges under tight schedules.

The ability to multi-task in a fast-paced environment is required to manage competing priorities and deadlines.

Nice to have

Experience with Cadence and Synopsys toolchains is beneficial for efficient analog design and verification flows.

Hands-on background with silicon bring up, testboard design, and scripted automation for characterization and debugging is a plus.

Understanding of Monte Carlo analysis, corner simulation, and yield validation for high-speed digital and analog interfaces is preferred.

Knowledge of standards bodies and participation in industry specification groups is a valuable contribution for long-term impact.

Practical notes

This role is hybrid with a requirement to work onsite at the Santa Clara, CA headquarters three days per week.

Typical interview steps

Hiring for engineering roles usually starts with a recruiter screen, followed by one or two technical rounds. Candidates often solve a coding problem, discuss past projects, and answer system design questions. Some loops include a take-home task. Final rounds typically cover team fit and give candidates a chance to ask questions. Interviewers look for how you break down an unfamiliar problem, not just whether you reach the answer. Practicing a few problems aloud and reviewing your own past projects are the best preparation.

Good to know

Analog design roles commonly involve schematic capture, simulation, and layout for complex circuits in advanced nodes.

Cadence and Synopsys toolchains are widely used in analog and mixed-signal design environments.

Monte Carlo analysis and corner simulation support robustness and yield validation for high-speed digital and analog interfaces.

Cross-functional collaboration is typical for hardware teams working on AI accelerator and system integration.

Silicon bring up often includes testboard design and scripted automation for characterization and debugging.

Career growth

Engineering careers usually progress from individual contributor to senior, staff, and principal levels. Some engineers move into management and lead teams of five to twenty people. Others stay on the technical track. Growth follows demonstrated impact, not tenure alone. A typical engineering ladder has clear levels with defined expectations for scope, quality, and mentorship. Moving up usually requires owning outcomes end to end rather than completing assigned tickets.