Senior Staff Analog Design Engineer

About the role

This role concentrates on analog and mixed-signic al integrated circuit design for AI inference accelerators and high-speed die-to-die interfaces. The position contributes to evaluation boards, silicon bring-up, and test feature development in a collaborative environment.

Software engineers turn product ideas into working code. Engineers work in small teams, review each other's work, and ship in small batches. Most teams follow agile practices such as sprints and daily standups. Engineers also write tests, fix bugs, and improve performance. The field values clear communication as much as technical skill. Engineers spend part of every week on planning, code review, and debugging, not just writing new code. The ability to explain a technical decision in plain words separates strong engineers from the rest.

Key facts

What you'll do

Circuit structures are defined through analog and mixed-signal integrated circuit design, using tools that include Cadence and Synopsys. Schematics are created and analyzed to assess system-level performance across process-voltage-temperature conditions.

Layout is refined to optimize low power and performance, and layouts are shared with backend engineers for integration. Design test benches are built and simulations are run to verify analog behavior for AI accelerator blocks.

Models of circuits are provided to support backend verification and tapeout activities. Monte-Carlo analysis is performed to ensure robustness across corners at six-sigma yield.

Evaluation boards are designed and used for silicon bring-up so that bench debug and characterization can occur. Scripts are built to automate silicon bring-up and to test key features on hardware.

Requirements

The posting states a minimum of 10 years of experience.

A completed BS/MS/PhD in Electrical Engineering is preferred, with required experience in high-speed circuit design blocks such as Phase Interpolator, Clocking, and PLL designs. High-speed circuit design experience must include years that align with the preferred degree level.

Schematic Capture, Spice Simulations, and Monte-Carlo simulations are required knowledge areas. Circuit Layout, Extraction, and back-annotated simulations must be part of the experience. Channel modeling using Matlab or equivalent tools is required.

Effective interpersonal and teamwork skills are required for cross-functional and cross-site collaboration. Excellent communication skills are required for participation in Standard bodies when relevant.

Practical notes

Work is hybrid, with 3-5 days per week onsite at the Santa Clara headquarters. Direct communication is valued within a respectful and inclusive culture. Typical interview steps

Hiring for engineering roles usually starts with a recruiter screen, followed by one or two technical rounds. Candidates often solve a coding problem, discuss past projects, and answer system design questions. Some loops include a take-home task. Final rounds typically cover team fit and give candidates a chance to ask questions. Interviewers look for how you break down an unfamiliar problem, not just whether you reach the answer. Practicing a few problems aloud and reviewing your own past projects are the best preparation.

Good to know

Analog design for digital accelerators relies on Cadence and Synopsys flows. Monte-Carlo analysis and corner verification are standard practices for yield assurance. Cross-site teamwork requires strong written and verbal communication. Evaluation boards enable rapid characterization of silicon behavior.

Career growth

Engineering careers usually progress from individual contributor to senior, staff, and principal levels. Some engineers move into management and lead teams of five to twenty people. Others stay on the technical track. Growth follows demonstrated impact, not tenure alone. A typical engineering ladder has clear levels with defined expectations for scope, quality, and mentorship. Moving up usually requires owning outcomes end to end rather than completing assigned tickets.