Analog Layout Designer

About the role

You will work closely with analog circuit designers to implement precision analog circuits that define the core performance of next-generation imaging systems. This role owns the full physical design flow for analog blocks, ensuring that circuit intent is preserved through careful layout strategies and rigorous verification. You will be responsible for optimizing circuit performance while controlling area, power, and parasitics within demanding specifications. The position requires disciplined execution of LVS, DRC, and parasitic extraction to tapeout quality standards. You will partner directly with design teams to debug layout versus schematic issues and iterate based on electrical validation results. Your work will directly influence the fidelity and reliability of high-voltage and low-noise analog paths in advanced CMOS processes. You will contribute to building reusable layouts and methodologies that support future product generations across embedded and medical imaging platforms.

Key facts

What you'll do

Perform precision analog physical design, including circuit layout, parasitic extraction, LVS, and DRC in strict accordance with design rules.

Collaborate closely with analog circuit designers to translate circuit schematics into robust, manufacturable layouts using the full suite of Cadence EDA tools.

Implement circuits in the TSMC 130nm BCD process, paying careful attention to high-voltage handling, low-noise requirements, and analog performance metrics.

Drive optimization of circuit performance, area, and power while maintaining yield and reliability targets for analog blocks.

Work independently and in close collaboration with circuit designers to resolve layout versus schematic discrepancies and timing issues.

Support tapeout activities by generating clean, well-documented layouts and verification reports that meet quality gates.

Utilize advanced layout techniques to control parasitics and ensure that extracted models match intended circuit behavior.

Maintain and evolve physical design methodologies to improve efficiency and reuse across analog and mixed-signal projects.

Verify that designs adhere to company security policies and handle proprietary information with care during all stages of tapeout.

Contribute to a culture of innovation by sharing best practices and proposing improvements to analog design flows and verification flows.

Participate in code reviews, design reviews, and cross-functional discussions to ensure alignment between circuit, layout, and system teams.

Apply creative problem-solving to overcome challenging analog constraints such as noise, matching, and high-voltage isolation.

Support the development of deliverables that enable third-party development and licensing through programs such as Butterfly Garden.

Demonstrate ownership of end-to-end tasks from layout integration to final signoff, ensuring that deliverables are ready for production.

Requirements

You must be legally authorized to work in the United States and not require sponsorship or transfer for employment visa status in the future.

This is a temporary position, and we are only considering candidates who do not now or in the future require sponsorship or transfer for employment visa status.

Butterfly Network does not accept agency resumes for this temporary position.

You must have expertise with circuit design and layout principles for high SNR precision analog circuits implemented in CMOS technology.

You must demonstrate expertise with both low voltage and high voltage designs exceeding 50 volts in mixed-signal environments.

You must be proficient with the full suite of Cadence EDA tools for layout, verification, and parasitic extraction.

You must be able to work both independently and in close collaboration with analog circuit designers and cross-functional teams.

You must adhere to all company security policies and complete all required security awareness training programs.

Practical notes

This role is a temporary position with an hourly rate of $100 per hour, up to 40 hours a week. The engagement details are specified in the source documentation and must be followed accordingly. Work location options include Burlington, MA Office; California

Hybrid; New York, NY Office, and these arrangements are defined in the source materials. Travel requirements are not specified in the provided source, so none are imposed beyond standard role expectations. Visa sponsorship is not available for this role, and candidates must meet the authorization requirements outlined in the qualifications section. The position is subject to E-Verify compliance as part of Butterfly Network Inc. policies.