Principal Silicon Verification Engineer

About the role

Graphcore builds advanced AI computing systems and data center hardware to drive innovation in machine learning. As part of the SoftBank Group, the company focuses on delivering high-performance, efficient silicon solutions. This role sits within the silicon design organization, ensuring that RTL matches architectural specifications for high-quality hardware delivery. The position requires ownership of the complete verification lifecycle for critical silicon components, driving confidence in functional correctness before tapeout. You will act as a technical leader who ensures that verification activities are rigorous, traceable, and aligned with project schedules. Success in this role depends on the ability to translate complex architectural intent into concrete verification strategies and testbench components. You will be accountable for closing difficult functional coverage points and resolving verification blockers that could impact tapeout decisions. This role demands a disciplined engineer who balances deep technical analysis with clear communication across global teams.

Key facts

What you'll do

• Execute verification tasks to meet quality standards for silicon delivery, ensuring that all test scenarios align with architectural requirements.
• Manage verification planning, specification development, and functional coverage closure to establish a clear roadmap for verification progress.
• Generate test cases and perform failure diagnosis and triage to isolate root causes and drive them to resolution efficiently.
• Provide technical feedback to hardware architects to influence design decisions and improve overall system robustness and performance.
• Contribute to the development of shared verification infrastructure, building reusable components and methodologies to accelerate future projects.
• Facilitate communication and collaboration across global engineering sites, ensuring that verification status and risks are transparent to all stakeholders.
• Drive the creation of directed, random, and formal verification environments using industry-standard methodologies and tools.
• Analyze complex functional failures and work with design teams to implement fixes that meet strict quality and schedule targets.
• Develop and maintain comprehensive testbenches that validate the correct interaction between hardware modules and interfaces.
• Define and track verification metrics that demonstrate confidence in the design and readiness for silicon validation in real systems.
• Mentor junior verification engineers and promote best practices in coding, verification methodology, and issue resolution.
• Participate in cross-functional design reviews to identify potential verification challenges early in the project lifecycle.

Requirements

• 12 to 14 years of professional engineering experience in verification roles with a strong track record of delivering complex silicon projects.
• Background in verification for ASIC or CPU environments, with a deep understanding of digital design fundamentals and verification techniques.
• Proficiency in SystemVerilog, Python, C++, and Linux, with the ability to write efficient, maintainable, and well-documented code.
• Proven ability to lead projects, plan verification cycles, and exercise independent judgment in making technical decisions.
• Strong problem-solving skills with the ability to identify the root cause of complex issues using systematic debugging methods.
• Ability to influence colleagues and clearly explain technical concepts to both technical and non-technical stakeholders.
• Self-motivated team player capable of working across different functional groups in a fast-paced, multi-site engineering environment.
• Demonstrated experience in managing verification schedules, risks, and dependencies while maintaining high-quality standards.

Nice to have

• Experience with UVM and SVA to build structured, reusable, and assertion-based verification environments.
• Knowledge of assembly languages to understand low-level code behavior and interface with firmware teams.
• Familiarity with LLVM, GCC, and Git to collaborate effectively on software tools and version-controlled verification assets.
• Experience with DRMS such as SGE for managing large-scale compute jobs and verification task scheduling.
• Proficiency in XML, XPath, XSLT, SQL, HTML, DOM, and Javascript to work with testbench infrastructure, data formats, and automation tools.

Practical notes

• This is a full-time position based in Bengaluru, India.
• Candidates must be eligible to work in India without visa sponsorship for this role.
• No relocation support or visa sponsorship is provided for this position.
• Travel requirements are limited to occasional domestic travel within India for project collaboration.
• The posting will remain open until the position is filled, and early application is encouraged due to high interest.
• Applicants should be prepared to demonstrate their verification expertise through technical discussions and practical examples during the interview process.