Staff/Principal Logical Design Engineer

About the role

Graphcore is actively seeking a highly skilled Staff or Principal Logical Design Engineer to join their cutting-edge Silicon department in Bristol. In this capacity, you will be responsible for the conception and articulation of high-quality micro-architecture specifications that form the bedrock of next-generation AI silicon. The position demands a deep partnership with engineering teams distributed across multiple locations to ensure the successful delivery of silicon tape-outs. You will own the intricate details of block-level implementations, translating abstract architectural concepts into precise and executable RTL constructs. This role is pivotal in bridging the gap between high-level design and physical implementation through rigorous specification and analysis. You will leverage your expertise to navigate complex design constraints and emerging technological challenges within the Graphcore architecture. Your work will directly influence the performance, power, and functionality of the company's flagship computational processors. Through meticulous analysis and cross-functional collaboration, you will ensure that the logical design integrity is maintained throughout the entire project lifecycle.

Key facts

What you'll do

• Investigate and formulate detailed micro-architecture specifications that define the behavior and structure of Graphcore's silicon components.
• Architect and implement Register Transfer Level (RTL) constructs using industry-standard hardware description languages to meet stringent performance targets.
• Orchestrate seamless communication channels between engineering teams located in different geographical areas to align on design objectives and constraints.
• Champion the development and maintenance of shared design infrastructure, methodologies, and automated engineering workflows to enhance team productivity.
• Apply a comprehensive suite of Electronic Design Automation (EDA) tools and the established Graphcore design flow to research and develop future silicon technologies.
• Execute rigorous block-level and chip-level verification processes, including but not limited to Linting, Synthesis, Timing Closure, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and functional coverage analysis.
• Liaise proactively with Physical Design, Verification, and DFT teams to identify and resolve cross-disciplinary issues early in the design cycle.
• Employ scripting and programming capabilities in languages such as Python or Tcl to automate tasks, debug complex design issues, and enhance verification efficiency.
• Demonstrate mastery of advanced digital design principles, specifically through the proficient use of SystemVerilog or VHDL for modeling and verification.
• Analyze and interpret digital design flows to optimize methodologies, ensuring adherence to Graphcore's strict quality and performance standards.

Requirements

• Hold a Bachelor's or Master's degree in Computer Science, Engineering, or a closely related technical field that provides a fundamental understanding of digital systems.
• Bring professional experience in digital design gained within a relevant industry setting, demonstrating a track record of successful project contributions.
• Exhibit a self-motivated and proactive mindset, capable of operating effectively both independently and within a collaborative team environment.
• Possess a proven history of collaborating across multidisciplinary teams to identify, analyze, and resolve intricate technical challenges.
• Show skill in leveraging programming scripts, particularly in Python or Tcl, to diagnose design issues, automate regressions, and support the debug process.
• Demonstrate strong proficiency in hardware description languages, specifically SystemVerilog or VHDL, for design implementation and verification activities.
• Develop a thorough understanding of complex digital design flows, from initial specification through to final tape-out, including synthesis and timing sign-off.
• Cultivate the ability to effectively manage personal workload, prioritize multiple concurrent tasks, and meet critical project deadlines in a fast-paced environment.

Nice to have

• Hands-on experience with processor design, including bus protocols and memory management units.
• A background in the design of application-specific blocks, such as systolic arrays or memory hierarchies.
• Familiarity with high-speed serial interfaces and their associated physical layer challenges.
• Experience integrating complex third-party IP blocks into a cohesive system design.
• Previous experience leading engineering teams or mentoring junior design engineers.
• Knowledge of arithmetic pipeline design techniques and their optimization.
• Expertise in floating-point arithmetic implementations and standards.
• Understanding of design for test (DFT) principles, including scan chain integration and testability features.
• Experience with synthesis tools and constraints-driven design methodologies.
• Background in static timing analysis (STA) and the use of timing verification tools.
• Knowledge of logical equivalence checking (LEC) flows to verify RTL consistency.
• Experience with detailed project planning, resource allocation, and risk management strategies.
• Understanding of power integrity analysis and its impact on the silicon design.
• Knowledge of semiconductor transistor characteristics and their influence on circuit-level design.

Practical notes

Graphcore offers a competitive salary, flexible working arrangements, and a generous annual leave policy. Benefits include private medical insurance, a health cash plan, dental plan, and a pension matched up to 5%. Life assurance, income protection, and a parental leave policy are also provided. The Bristol office provides healthy food options, snacks, and a barista bar. Graphcore is committed to maintaining an inclusive environment and can provide reasonable adjustments for candidates during the interview process.