DFT Engineer

About the role

Graphcore is expanding its dedicated Silicon team and is seeking a DFT Engineer to contribute directly to the definition and implementation of testability for next-generation AI processors targeted at demanding datacenter applications. In this role, you will take ownership of shaping the testability architecture from the earliest design stages, ensuring that the silicon is built with diagnostics and debug capabilities that support high yield and field reliability. You will work at the intersection of design and verification, collaborating closely with design, verification, physical design, and product engineering teams to embed test requirements and constraints throughout the project lifecycle. The position exists within the broader context of the SoftBank Group ecosystem, which provides long-term investment supporting the company's AI compute roadmap and product ambitions. You will be responsible for defining and driving the execution of DFT features, methodologies, and flows that enable efficient validation from pre-silicon through to silicon bring-up and production testing. This role requires a methodical approach to problem solving, strong ownership of test infrastructure, and the ability to influence both specification and implementation details. You will contribute to the continuous improvement of DFT practices by tracking emerging industry techniques and tools, and by introducing those that are relevant to Graphcore's advanced processor designs.

Key facts

What you'll do

• Define the DFT architecture, scan chains, clock control, and test access mechanisms for upcoming AI chip designs while coordinating closely with verification engineers to validate testability features.
• Build, maintain, and scale DFT flows and methodologies that integrate with the broader silicon design process, ensuring consistency, automation, and adherence to project timelines.
• Partner with design, verification, physical design, and product engineering teams to embed testability requirements, test modes, and diagnostic structures throughout the project from specification to tapeout.
• Integrate third-party IP blocks into the existing DFT infrastructure, ensuring that scan chains, boundary scan, and other test structures are correctly connected and controllable.
• Create structural test vectors, perform coverage analysis, and drive closure activities to improve fault coverage and reduce test time or area overhead.
• Collaborate with product and test engineering teams during silicon bring-up, diagnosing failures observed at probe, correlating them with simulation and structural models, and accelerating yield learning.
• Track industry developments in the field of DFT, such as new compression schemes, IJTAG-based instrumentation, and emerging standards, and introduce relevant techniques and tools when appropriate.
• Develop and maintain test plans, DFT specifications, and documentation that clearly describe the intended test strategy, coverage goals, and implementation details for each design.
• Implement and verify scan, boundary scan, and core test features in register transfer level (RTL) to support structured and compressed test patterns.
• Support the creation and optimization of test compression hardware, including selecting compression architectures and evaluating their impact on area, power, and test throughput.
• Participate in the definition of clock and reset strategies for test modes, ensuring that scan shifting, capture, and release sequences operate correctly across voltage and frequency states.
• Work with ATPG tools to generate, optimize, and debug test patterns, and collaborate with pattern verification engineers to ensure high quality and efficient test sets.
• Perform gate-level simulation using EDA tools such as Synopsys VCS and waveform analysis with Verdi to debug test infrastructure and resolve functional issues.
• Coordinate with physical design teams to address issues related to scan insertion, power network planning, clock gating, and test mode control during implementation.
• Support the qualification and characterization of production test programs, contributing to the development of efficient and reliable test methodologies for high-volume manufacturing.

Requirements

• Hold a degree in Computer Science, Electrical Engineering, or a related technical discipline, or possess equivalent practical experience.
• Demonstrate a strong grasp of fundamental DFT building blocks including JTAG (IEEE 1149.1), IJTAG (IEEE P1687), Core Test (IEEE P1500), Streaming Scan Network, test compression, and Observed Control Cells (OCC).
• Have a background in writing detailed DFT specifications and leading the implementation of DFT features from architecture through to integration.
• Show familiarity with design verification approaches for validating DFT features through pre-silicon simulation and testbench development.
• Possess practical experience with scan-based testing methodologies and the use of standard automatic test pattern generation (ATPG) tools.
• Show knowledge of ATPG pattern verification flows, including the use of gate-level simulation with Synopsys VCS, waveform analysis with Verdi, or comparable EDA software.
• Maintain a solid understanding of digital integrated circuits and systems, including timing, power, and signal integrity considerations relevant to test modes.
• Demonstrate hands-on Verilog RTL coding ability, with familiarity in SystemVerilog for implementing and debugging test infrastructure.
• Exhibit proficiency in scripting and debugging using languages and tools such as Python, TCL, Perl, or Shell to automate flows and analyze results.
• Have direct experience in at least one of the following areas: RTL design, simulation and debug, synthesis, or static timing analysis (STA).

Nice to have

• Experience implementing and verifying MBIST and BISR techniques for embedded memory and logic test infrastructure.
• Exposure to STA constraint development and analysis for DFT modes, including the creation and interpretation of SDF-based simulations.

Practical notes

• This is a full-time position.
• Candidates must be eligible to work in the United Kingdom.
• Visa sponsorship may be considered for suitable candidates based on role and location.
• Travel may be required between office locations in Bristol and Cambridge.
• Applications will be reviewed on a rolling basis until the role is filled.
• The position requires the ability to work collaboratively in a fast-paced, technically challenging environment.