Senior Physical Design Engineer

About the role

You will architect and execute the physical implementation strategy for multi-million gate System-on-Chip (SoC) designs that power the core connectivity stack of our LEO satellite constellation. This role demands a deep partnership with front-end design and verification engineers to translate register transfer level (RTL) intent into a robust, manufacturable physical layout. You will own the end-to-end flow for advanced semiconductor nodes, ensuring that power, performance, and area (PPA) targets are met without compromising timing sign-off or manufacturability rules. The position requires a meticulous approach to design rule checks (DRC) and layout versus schematic (LVS) verification to guarantee zero-defect tape-outs. You will lead the optimization of clock tree synthesis (CTS) and placement strategies to mitigate cross-talk and electromigration risks in high-frequency interfaces. In addition, you will implement rigorous physical verification methodologies and debug complex post-layout netlist issues to ensure the design is ready for tape-out. You will collaborate with systems architects to understand high-level specifications and make informed physical design decisions that align with mission objectives. This role is critical in de-risking the tape-out process and ensuring that the silicon efficiently supports secure, low-latency global IoT connectivity.

Key facts

What you'll do

Architect the floorplan and power grid infrastructure for complex SoC designs, analyzing macro placement and I/O configuration to optimize for congestion and signal integrity.

Lead the implementation of clock distribution networks, performing detailed CTS planning and optimization to minimize skew and latency across the die.

Execute physical verification sign-off, including DRC, LVS, and electrical rule checks (ERC), to ensure the layout strictly adheres to process design rules and schematic fidelity.

Perform gate-level and post-layout static timing analysis, identifying and resolving timing violations through strategic buffer insertion and logic restructuring.

Manage the integration and placement of standard cells, macros, and IP blocks to meet density, timing, and power constraints of advanced nodes.

Collaborate with verification and functional teams to debug physical-level issues, correlating layout parasitics with functional failures or performance deviations.

Utilize scripting and automation to enhance flow efficiency, reduce manual errors, and scale verification processes across design variants.

Guide the selection and configuration of EDA tools to ensure the physical design flow is robust, scalable, and aligned with industry best practices.

Perform analysis on power delivery networks, ensuring that voltage drop and electromigration criteria are satisfied across all operating modes.

Support the development of test structures and debug methodologies to validate yield and reliability before final tape-out.

Coordinate with packaging and thermal engineering teams to ensure the die design is compatible with assembly and meets thermal budgets.

Own the generation of final production databases, ensuring that the GDSII output is accurate, well-documented, and ready for tape-out.

Mentor junior physical design engineers on best practices, flow execution, and problem-solving techniques to elevate team capability.

Drive the adoption of advanced node methodologies, ensuring that the design is manufacturable and yields predictable results at scale.

Requirements

Candidates must possess a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field with a strong emphasis on physical design methodology.

You must have a proven track record of delivering physical design for production in ASICs targeting 7nm, 5nm, or more advanced process nodes, demonstrating mastery of FinFET-based implementation flows.

A minimum of eight years of hands-on experience in physical design, place and route, and timing closure for complex digital designs is mandatory.

You must be proficient in industry-standard tools such as Synopsys ICC2, Innovus, or Cadence Genus and have deep expertise in performing sign-off using tools like PrimeTime and Calibre.

You must have extensive experience with power analysis and optimization, including the use of tools such as PrimeTime PX or similar platforms to validate IR drop and electromigration.

You must demonstrate a thorough understanding of clock domain crossing (CDC) analysis and multi-clock domain synchronization techniques to ensure functional correctness across the die.

You must have a strong grasp of low-power design techniques, including the implementation and verification of power domains, retention strategies, and power gating methodologies.

You must be able to interpret and debug timing reports, waveform analyses, and ECO fix logs to drive rapid resolution of critical issues.

Nice to have

Experience with satellite or aerospace communication systems is highly valued, as this role directly supports LEO payload and gateway development.

Familiarity with security-focused design principles and hardware obfuscation techniques is preferred due to the sensitive nature of secure global communications.

Practical notes

This is a full-time onsite role based in Saratoga, California.

Candidates must be eligible to work in the United States without sponsorship at this time.

The role requires collaboration across distributed engineering teams across time zones, requiring reliable connectivity and flexible scheduling.