Principal DV Engineer

About the role

Position Available: Digital Design Verification Engineer

E-Space is actively constructing a next-generation low Earth orbit (LEO) infrastructure. This network is designed to deliver secure, universally accessible connectivity for Internet of Things (IoT) applications. Our mission involves reshaping the economic and operational models for satellite and terrestrial communications. The company maintains a commitment to innovation, aiming to expand global economic capacity and protect the space environment.

We are currently recruiting a Digital Design Verification Engineer to join our team in Saratoga, California. This is a full-time position offering a salary range of 160,000 USD to 180,000 USD. The successful candidate will play a critical role in ensuring the reliability of our custom application-specific integrated circuits (ASICs).

In this capacity, you will be responsible for defining the verification strategy for orbital hardware. This involves creating directed tests and coverage models specifically for satellite-focused chips. A key part of the role is driving automation that leverages artificial intelligence (AI) tools to accelerate verification cycles. You will ensure that our designs meet stringent protocol standards and perform reliably in the unique conditions of space.

Key Responsibilities

Your daily work will involve several critical tasks. You will architect test frameworks to ensure protocol compliance for wireless telephony silicon. This includes designing stimulus modules that validate custom ASIC behavior under simulated orbital conditions. You will guide the development of automation pipelines that effectively integrate AI assistance into existing verification workflows.

Modeling complex bus interactions using SystemVerilog will be essential to confirm data integrity. You will collaborate closely with system architects to translate mission requirements into concrete test cases. Verification of communication IP blocks will be performed using UVM components and constrained random methods. Your analysis of verification results will identify functional gaps and direct regression updates. Ultimately, you will confirm design readiness through formal checks and targeted testing for satellite hardware.

Required Qualifications

To succeed in this role, you must possess a strong foundation in hardware description languages. A mandatory requirement is your knowledge of Verilog, SystemVerilog, and the Universal Verification Methodology (UVM). This expertise is necessary to build dependable testbenches. While not required, an understanding of VHDL is valuable when reviewing existing satellite communication models.

You must bring three years of professional experience in digital verification, specifically for space or wireless projects. Your background should demonstrate a history of delivering high-quality verification results in these specialized domains.

Preferred Qualifications

Experience with AI tools that can accelerate test development and debugging is a significant advantage. Familiarity with environments where AI assists in verification flow is highly desirable.

Technical Skills

• Verilog
• SystemVerilog
• Universal Verification Methodology (UVM)
• VHDL

Practical Information

Please Ensure all details are current before submitting your materials. This role represents a key opportunity to contribute to a transformative space-based connectivity project.

What you'll do

You will define the verification strategy for orbital hardware, establishing a robust framework that ensures the highest levels of reliability for our satellite ASICs. This ownership includes creating directed tests and sophisticated coverage models that are specifically tailored to the demanding constraints of space communication chips. A core part of your mission will be to architect and drive the automation of verification flows, leveraging artificial intelligence tools to significantly compress development cycles and enhance productivity. You will model intricate bus interactions using SystemVerilog to rigorously validate data integrity across complex communication pathways.

You will work in close collaboration with system architects to meticulously translate high-level mission requirements into detailed, executable test cases that leave no functional gap unexamined. The verification of communication IP blocks will be executed with precision using UVM components and advanced constrained random methodologies to uncover edge-case behaviors. You will conduct in-depth analysis of verification results to identify latent functional gaps and proactively direct the evolution of regression suites. Your work will involve building and maintaining scalable verification environments that integrate AI assistance seamlessly into the existing workflow. Ultimately, you will provide the final confirmation of design readiness through rigorous formal checks and exhaustive testing specifically designed for the satellite hardware environment.

You will architect test frameworks to guarantee strict protocol compliance for wireless telephony silicon, ensuring that every signal and waveform adheres to the required specifications. This responsibility involves the design of comprehensive stimulus modules capable of validating custom ASIC behavior under a wide array of simulated orbital conditions, including extreme temperature and radiation effects. You will guide the development and deployment of automation pipelines that effectively weave AI assistance into the fabric of our verification workflows, reducing manual overhead and increasing coverage.

Your expertise in SystemVerilog will be essential for modeling complex bus transactions and interfaces, confirming that data remains intact and uncorrupted during high-speed operations. You will partner with system architects to deconstruct mission requirements and convert them into concrete, testable vectors that verify functionality under all anticipated scenarios. The verification of communication IP blocks will rely on UVM components and constrained random methods to achieve the statistical confidence required for spaceflight hardware. You will analyze intricate verification data to pinpoint functional deficiencies and direct the necessary updates to regression tests.

You will ultimately confirm that the design is ready for flight by executing formal verification checks and targeted tests that mirror the harsh realities of the orbital environment. This role demands a high level of discipline and ingenuity to ensure that the silicon operating in our satellites performs flawlessly once deployed. You will be instrumental in building the verification infrastructure that supports the next generation of secure, low-earth orbit connectivity.

Requirements

A strong foundation in hardware description languages is essential for success in this position. You must possess mandatory knowledge of Verilog, SystemVerilog, and the Universal Verification Methodology (UVM) to construct dependable and scalable testbenches. While not a core requirement, an understanding of VHDL is considered valuable for reviewing and integrating with existing satellite communication models.

You are required to bring a minimum of three years of professional experience specifically in digital verification. This experience must be rooted in space or wireless project domains, demonstrating your ability to navigate the unique challenges of these specialized fields. Your professional history must showcase a consistent ability to deliver high-quality verification results that meet the rigorous standards of the industry.

You must be able to demonstrate proficiency in the core technical languages and methodologies outlined in the technical skills section. Your background should include practical experience building testbenches and running simulations that validate complex digital circuits. A proven track record of identifying and resolving verification issues early in the design cycle is critical. You must be comfortable working within a fast-paced, collaborative environment where clear communication and meticulous attention to detail are paramount.

Nice to have

Experience with AI tools that accelerate test development and debugging represents a significant advantage in this role. Familiarity with verification environments where AI is integrated into the flow is highly desirable and reflects the forward-looking nature of our engineering practices.

Practical notes

This role is based in Saratoga, California and is a full-time engagement. The compensation for this position is structured within a range of 160,000 USD to 180,000 USD. Please ensure that all details within your application materials are current and accurate. This position presents a unique opportunity to contribute directly to a transformative space-based connectivity project that is reshaping global communication models.