Senior Digital Hardware Design Engineer

About the role

Digital Hardware Design Engineer, LEO IoT Constellation

Position Overview

E-Space is constructing a next-generation low Earth orbit (LEO) network intended to deliver secure, actionable connectivity for the Internet of Things on a global scale. This role is central to that mission, focusing on the creation of digital hardware that forms the core of our satellite communication nodes. You will be responsible for translating high-level system requirements into robust, silicon-ready designs capable of withstanding the rigors of orbit. The work demands a meticulous approach to signal integrity, power management, and verification, ensuring that our hardware meets exacting standards for performance and reliability before physical production.

This is a hands-on engineering position where your expertise will directly influence the architecture of our space-based infrastructure. You will work at the intersection of digital logic, communication protocols, and physical constraints, ensuring that our custom hardware is both functional and manufacturable. The position requires a deep understanding of digital design principles and a commitment to validating designs through rigorous verification methodologies. Collaboration is integral, as you will partner with firmware, systems, and manufacturing teams to ensure seamless integration from logic gates to deployed satellites.

Key Responsibilities

You will architect critical signal pathways within custom satellite hardware, carefully managing power budgets and electromagnetic compatibility to ensure reliable operation in the space environment. A primary duty involves designing and implementing verification strategies, including comprehensive testbenches, to identify and resolve design flaws prior to tapeout. You will coordinate closely with firmware engineers to define, validate, and optimize register maps and communication protocols, ensuring that digital logic aligns perfectly with software expectations.

The role involves guiding the creation of detailed technical documentation that captures design decisions, trade-offs, and rationale for future engineering teams. You will perform in-depth synthesis constraints implementation and static timing analysis to guarantee that designs meet stringent operational frequency and latency targets. Supporting laboratory measurements is a key function, where you will correlate simulation predictions with the electrical behavior of actual hardware on development boards. Evaluating alternative components and interfaces is also essential, allowing the team to balance technical capability, risk, and cost-effectiveness. Finally, you will partner with manufacturing specialists to ensure that designs are testable, scalable, and robust for high-volume production.

Essential Qualifications

To be considered, you must possess authorization to work in the United Kingdom. A minimum of three years of professional experience in digital design is required, demonstrating a proven track record of delivering complex digital hardware. Expert-level proficiency with Verilog or SystemVerilog is a mandatory requirement for this position. You must have substantial familiarity with field programmable gate arrays, particularly regarding their implementation and debugging during development cycles. A strong understanding of communication protocols is necessary to effectively integrate digital subsystems within a larger satellite architecture.

The ability to independently interpret complex datasheets and technical data sheets is non-negotiable for success in this role. You must be highly proficient with version control systems and collaborative engineering tools to manage design artifacts and revisions. A disciplined approach is expected, with the ability to follow defined development processes while actively seeking improvements and optimizations.

Preferred Experience and Skills

Candidates with direct experience in satellite applications or projects involving harsh environmental conditions hold a distinct advantage. A background in aerospace, defense, or telecommunications infrastructure is highly relevant.

Core technical skills required for this position include a strong command of Verilog, SystemVerilog, and FPGA development. You will utilize testbenches for functional verification and operate within a version-controlled environment. Familiarity with synthesis and timing analysis toolchains is expected.

Practical Information

This position is based in Loughborough and is offered as a full-time engagement. The starting compensation for this role is 70,000 GBP per year. Before proceeding, please confirm all details regarding the role on the official application page. We are committed to building a diverse team and encourage applications from all qualified individuals.