Senior DFT Engineer

About the role

E-Space operates at the intersection of terrestrial infrastructure and orbital platforms, delivering connectivity from low Earth orbit. Our mission is to make connectivity universally accessible, secure, and actionable for global economies. We are constructing a next-generation low Earth orbit (LEO) satellite system to transform the economics and design of Internet of Things (IoT) communications. This role exists within a mission to innovate space-based communications, produce actionable intelligence, protect our planet, and elevate the quality of life. We are seeking a Senior Design-for-Test (DFT) Engineer to join our System-on-Chip (SoC) design team. The Senior Design-for-Test Engineer is responsible for defining and implementing comprehensive test strategies for complex digital SoC designs that target applications in 5G infrastructure, IoT devices, and LEO satellite communications. You will own the methodology for test insertion, diagnosis flows, and yield analysis to validate design integrity, ensuring robust testability and quality of silicon from initial design phases through high-volume manufacturing. Collaboration with design, firmware, and manufacturing teams is central to ensuring test coverage from prototype through production scale-up, and you will establish scan chain layouts while defining fault models for digital modules within orbital communication hardware.

Key facts

What you'll do

• Analyze complex digital modules to define fault models and establish scan chain layouts that align with orbital communication hardware requirements.
• Implement structured test methods and logic built-in self test (BIST) features across heterogeneous compute blocks to optimize test coverage and reduce silicon risk.
• Generate verification testbenches that mirror production test patterns to enable early silicon validation and reduce iteration cycles.
• Coordinate with manufacturing teams to align test program timing with production volume requirements and yield goals, ensuring seamless transitions from prototype to scale-up.
• Design compression and decompression schemes to minimize tester memory footprint and reduce overall test cycle count, improving test efficiency.
• Partner with firmware engineers to ensure alignment between embedded instrumentation and system-level test objectives, creating cohesive validation strategies.
• Perform analysis of test data to identify process variations, feeding results directly into design refinement loops for continuous improvement.
• Maintain comprehensive documentation for test methodology, coverage metrics, and failure modes to support compliance records and audits.
• Utilize ATPG tools and strategic scan chain implementation to meet strict test coverage and yield objectives for digital designs.
• Interpret technical datasheets and specifications for complex communication devices to inform test strategy and validation plans.

Requirements

• Hold a Bachelor's or Master's degree in Electrical Engineering or a closely related technical field.
• Possess a minimum of 3 to 5 years of professional experience in digital test implementation for semiconductor projects.
• Demonstrate expertise in scan chain insertion, automatic test pattern generation (ATPG) tools, and fault simulation methodologies.
• Show proficiency in register transfer level coding using Verilog or VHDL, along with synthesis constraints flows.
• Exhibit the ability to interpret technical datasheets and specifications for complex communication devices.
• Apply a foundational understanding of silicon behavior and test response analysis to succeed in this demanding position.
• Confirm eligibility to work in the United States without sponsorship for this role.
• Commit to a full-time schedule based in Saratoga, California, with no remote work options available.

Nice to have

• Experience with radiation-tolerant or space-qualified semiconductor design practices is highly valued.
• Familiarity with the unique challenges of the space environment and relevant quality standards will accelerate contributions in this role.

Practical notes

• The position is based in Saratoga, California.
• It is a full-time engagement with an annual compensation package of $170,000.
• Prospective candidates should confirm specific application procedures and requirements on the official company career page.
• Candidates must be able to start immediately and commit to the full-time schedule without remote work flexibility.