Principal Signal Integrity Engineer

About the role

You will serve as the definitive technical authority for electrical integrity across d-Matrix's high-performance AI compute platforms, owning the full lifecycle of signal and power integrity validation. In an environment pushing 112G/224G SerDes while delivering massive currents to multi-chip modules, your analysis will directly determine whether our Digital In-Memory Computing architecture meets stability and performance targets. You will own the end-to-end modeling, simulation, and correlation activities that bridge silicon behavior with system-level reliability. Your work will ensure that package-level parasitics and board-level implementations do not compromise the intended electrical behavior of the design. You will define and enforce the methodologies that allow our hardware to scale efficiently under demanding AI workloads. By translating complex electrical behavior into actionable design rules, you will enable the broader team to execute with confidence and precision.

Key facts

What you'll do

Lead the SI/PI strategy for next-generation AI accelerators, concentrating on high-speed interfaces such as PCIe Gen6/7 and CXL, as well as custom Chiplet-to-Chiplet interconnect implementations.

Model and analyze complex multi-chip packages, including detailed interposer routing, micro-bump parasitic extraction, and die-to-die link budgeting to ensure robust electrical performance.

Design and optimize the Power Delivery Network (PDN) to satisfy stringent Z_Target requirements, performing transient analysis to maintain voltage stability during rapid and massive AI workload transitions.

Execute comprehensive channel simulations both pre- and post-layout using IBIS-AMI models, establishing jitter, crosstalk, and loss budgets for 112G and beyond.

Lead the correlation of simulation results with laboratory measurements using VNA, TDR, and high-speed oscilloscope data to validate and refine design accuracy.

Translate challenging simulation outcomes into clear, actionable physical layout constraints for the PCB design team, specifically for advanced stack-ups and high-density routing schemes.

Act as the subject matter expert to mentor hardware and layout engineers on SI/PI best practices and advanced mitigation techniques such as skip-vias, voiding strategies, and material selection.

Define measurement methodologies and test setups that align with system-level performance goals and manufacturing requirements.

Drive the creation of reusable analysis models and scripts that improve the efficiency and accuracy of future design iterations.

Collaborate closely with cross-functional teams to ensure that signal integrity and power integrity objectives are met without compromising schedule or cost targets.

Contribute to the development and maintenance of internal standards and documentation that ensure consistency across all AI compute hardware platforms.

Support the qualification and validation of new silicon and system integrations from an electrical integrity perspective.

Identify and mitigate potential risks related to signal degradation, power noise, and electromagnetic interference before they impact product yield or performance.

Champion the adoption of advanced SI/PI tools and flows that improve predictability and reduce iteration time within the design cycle.

Requirements

You hold an MS or PhD in Electrical Engineering or a related field with a focus on Electromagnetics or Signal Integrity.

You bring 12 or more years of dedicated SI/PI design experience within high-performance networking, GPU, or server platforms.

You demonstrate expert-level mastery of industry-standard simulation tools, including SI tools such as Ansys HFSS, Cadence Sigrity, Keysight ADS, or Simbeor, and PI tools such as Ansys SIwave, Cadence PowerSI, or CST.

You possess a proven track record working with 112G SerDes and high-speed memory architectures, including a deep understanding of PAM4 signaling and the impact of Forward Error Correction on link margins.

You have hands-on experience using 50GHz or higher VNAs, time-domain reflectometers, and real-time or sampling oscilloscopes for measurement and validation.

You are capable of performing advanced electromagnetic analysis, including extraction of parasitic elements and interpretation of field solvers for complex interconnect structures.

You can interpret and apply PCB material science concepts, including understanding glass weave effects, skin effect loss mechanisms, and copper roughness modeling.

You exhibit strong analytical rigor and the ability to correlate theoretical models with measured data to close the loop on design accuracy.

Nice to have

Knowledge of PCB material science, including glass weave effects, skin effect loss, and copper roughness modeling.

Experience with Python or MATLAB for post-processing large simulation datasets and automating sweep analysis.

Familiarity with OCP (Open Compute Project) hardware specifications for AI modules.

Practical notes

The role is based in Santa Clara.

Employment is full-time.

d-Matrix is an equal opportunity employer and does not accept resumes or candidate submissions from external agencies.