Senior Staff Design Verification Engineer

About the role

This role defines and validates next generation in-memory compute arrays for AI workloads. The position shapes verification strategy and execution within a collaborative, fast paced startup. Success depends on direct communication, humility, and shared problem solving.

Software engineers turn product ideas into working code. Engineers work in small teams, review each other's work, and ship in small batches. Most teams follow agile practices such as sprints and daily standups. Engineers also write tests, fix bugs, and improve performance. The field values clear communication as much as technical skill. Engineers spend part of every week on planning, code review, and debugging, not just writing new code. The ability to explain a technical decision in plain words separates strong engineers from the rest.

Key facts

What you'll do

Architectural specifications are translated into directed verification plans that cover system behavior from design through integration. Verification results are documented and shared to support design decisions and tape out readiness. Testbenches are built and maintained using UVM/OVM methodologies to ensure reusable coverage of SoC features. SoC design verification tests are implemented, debugged, and executed to validate functionality before silicon bring up. SystemVerilog randomization, coverage, and assertions are authored to enforce protocol compliance and corner case behavior. Cross functional collaboration with design and product teams clarifies requirements and reduces integration risk for AI driven workloads. C/C++ and SystemC interfaces are exercised where applicable to validate hardware software interaction paths. The role supports leadership of verification environments and tape out efforts across multiple projects.

Requirements

A degree in Electrical Engineering, Computer Science, or a related field is required. At least 12 years of industry experience is required for a BS, or at least 7 years for an MS. Hands on experience with SoC verification from architecture through tape out and bring up is required. Fluency with SystemVerilog randomization, coverage, and assertions methodology is required. Practical ASIC SoC design verification tests and debug experience are required. Fluency with UVM OVM or VMM verification methodology is required. Strong problem solving skills and a passion for AI domain challenges are required.

Practical notes

Work is hybrid, with three onsite days per week at the Santa Clara, CA headquarters. Typical interview steps

Hiring for engineering roles usually starts with a recruiter screen, followed by one or two technical rounds. Candidates often solve a coding problem, discuss past projects, and answer system design questions. Some loops include a take-home task. Final rounds typically cover team fit and give candidates a chance to ask questions. Interviewers look for how you break down an unfamiliar problem, not just whether you reach the answer. Practicing a few problems aloud and reviewing your own past projects are the best preparation.

Good to know

Verification focused roles rely on precise constraints, assertions, and coverage to validate complex hardware behavior. In memory computing architectures introduce new modeling challenges for testbenches and simulation performance. UVM and related methodologies remain central to modern SoC verification flows in semiconductor startups. Teams communicate directly to resolve issues and keep tape out schedules on track.

Career growth

Engineering careers usually progress from individual contributor to senior, staff, and principal levels. Some engineers move into management and lead teams of five to twenty people. Others stay on the technical track. Growth follows demonstrated impact, not tenure alone. A typical engineering ladder has clear levels with defined expectations for scope, quality, and mentorship. Moving up usually requires owning outcomes end to end rather than completing assigned tickets.