Staff Engineer, SoC Architecture - Memory Subsystem and Interconnect

About the role

The Staff Engineer, SoC Architecture - Memory Subsystem and Interconnect drives the architectural direction of next-generation System-on-Chips at Samsung Research America, owning the critical memory subsystem and interconnect roadmap. This role owns the end-to-end architecture of the Fabric, System Cache, and DRAM Controller, translating complex workload requirements into concrete microarchitectural solutions. You will define the performance, power, and area tradeoffs for these subsystems, ensuring they meet the demanding needs of future Galaxy flagship products across smartphones and tablets. The position requires hands-on leadership in guiding the development of innovative architectural features that boost throughput, reduce latency, and optimize energy efficiency. You will serve as the primary technical authority, evaluating proposals and communicating intricate architectural decisions to diverse engineering audiences, including hardware, software, and leadership teams. Collaboration is central to this role, as you will work closely with silicon bring-up teams, product developers, and global R&D partners to ensure architectural viability and debug issues from analysis to tapeout. Ultimately, your work will directly influence the capabilities and user experience of Samsung's flagship mobile and future computing devices by shaping the core infrastructure that connects processors and memory.

Key facts

What you'll do

Architect and define the high-level architecture and microarchitecture for the Fabric, System Cache, and DRAM Controller subsystems within next-generation SoCs.

Lead the development of innovative architectural features designed to enhance power performance and efficiency for targeted workloads in Samsung's flagship products.

Evaluate and deliver architecture proposals for products in new and existing markets, considering tradeoffs in performance, area, and power.

Perform high-level performance modeling, simulation, and analysis to assess the impact of new Fabric, Cache, and DRAM controller features on complex use cases and benchmarks.

Drive performance studies and analysis to support the inclusion of new microarchitectural features, ensuring they meet stringent goals for performance, latency, and power.

Collaborate with a global team of SoC Architects to communicate evaluation results and architectural decisions across hardware, software, and leadership audiences.

Work directly with silicon bring-up and product teams to verify architectural proposals, debug issues, and ensure the successful implementation of the memory subsystem and interconnect.

Document detailed architecture and microarchitecture specifications, creating clear documentation for design teams and contributing to the broader architecture community.

Partner with cross-functional groups including drivers, operating systems, and system software to ensure cohesive integration of memory and interconnect features throughout the SOC.

Champion the analysis of memory controller architecture, including memory scheduling, prioritization mechanisms, and Quality of Service (QoS) implementations.

Provide deep expertise in ARM bus infrastructures such as ACE, AXI, and AHB, guiding their application within complex SoC designs.

Leverage detailed knowledge of JEDEC standards for LPDDR, DDR, and HBM to analyze specifications and drive memory subsystem recommendations that meet industry standards.

Apply a strong background in memory systems and computer architecture to understand and optimize tradeoffs among memory bandwidth, latency, performance, power, and SoC area.

Utilize experience with specialized tools such as the BookSim Simulator and Platform Architect to model and analyze complex memory subsystem behaviors.

Requirements

BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience.

Possess 8+ years of experience in SOC or ASIC design and architecture.

Have prior direct experience exceeding 5 years in Fabric, System Cache, or DRAM Controller Architecture or microarchitecture.

Demonstrate a thorough understanding of memory controller architecture, including memory scheduling, prioritization techniques, and Quality of Service (QoS) policies.

Show detailed knowledge of ARM bus infrastructure, specifically protocols such as ACE, AXI, and AHB.

Exhibit fluid knowledge of one or more JEDEC standards, such as LPDDR, DDR, or HBM, and the ability to analyze these standards to formulate and drive technical recommendations.

Possess a background in memory systems and computer architecture sufficient to understand and analyze tradeoffs among memory bandwidth, latency, performance, power consumption, and SoC area.

Demonstrate the ability to collaborate effectively with cross-functional teams, including hardware engineers, software developers, and technology leadership.

Nice to have

Experience utilizing the BookSim Simulator for architectural modeling and analysis.

Experience with the Platform Architect tool for system-level exploration and performance evaluation.

Practical notes

This is a full-time position based in the United States.

Applicants must be eligible to work in the country where the position is located without requiring sponsorship now or in the future.

Visa sponsorship is not available for this role.

Relocation is not offered.

Travel is not expected for this role.