Power Validation Engineer

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are looking for a Power Validation Engineer to own the end-to-end power characterization of our ASIC and the mezzanine card platform - from early silicon bring-up through production qualification. You will design measurement methodology, build test benches, and drive findings directly into silicon, package, and system design decisions.

Key Responsibilities

- Design and execute power measurement campaigns across all voltage rails (VDD_CORE, HBM, PCIe, AUX, etc) under realistic LLM inference and power virus workloads; characterize peak, sustained, and idle power envelopes across PVT corners and define derating curves used in system thermal and PDN specs

- Validate power delivery network (PDN) performance - VRM load step response, PCIe power compliance, PDN impedance - and translate measurements into actionable feedback on capacitor placement, plane geometry, and de-cap strategy for PCB and package design teams

- Profile power transient events (ramp rates, droop amplitudes, recovery profiles) and correlate them with on-die performance monitor data; build automated power sweep frameworks exercising the full inference workload space across model sizes, batch sizes, sequence lengths, and precision modes

- Run extended stress workloads (72 h+ continuous) to surface reliability risks and throttling behavior; instrument multi-zone thermal profiles and support our overseas partners with SLT, production and debugging.

- Validate power sequencing, PMBus telemetry accuracy, and BMC alert thresholds across cold-start, hot-restart, and fault-injection scenarios; own power-related pass/fail criteria across FAT, SFT, and RIN qualification stages

- Feed characterization data back to RTL and physical design teams as input for DVFS policy, clock gating coverage, and leakage optimization; write precise validation reports that enable silicon and firmware teams to act without re-running experiments

- Lead the electrical characterization, validation, and qualification process for the on-board system-level power distribution network, spanning from power converter design to ASIC power integrity validation.

- Provide critical support to design engineers through debug, component validation, and failure analysis for released products, independently troubleshooting and determining the root cause of electrical component defects and design flaws.

- Develop and implement automated/scripted test procedures for the general qualification and testing of Devices Under Test (DUTs) as part of a comprehensive automation suite.

- Collect, analyze, and aggregate test data to support data-driven engineering decisions, generate reports on findings, reduce data sets, and thoroughly investigate test outcomes down to the hardware interface or component level.

- Collaborate with hardware designers and diagnostics development teams to understand new project architectures and system components, ensuring the necessary support for testing and debug efforts is implemented.

You may be a good fit if you have (Must-have qualifications)

- A Bachelor's degree in Electrical Engineering or a related field. Advanced degrees or certifications in power electronics or related areas are a plus

- Deep understanding of ASIC and system-level power delivery - VRM topology, PDN impedance, decoupling strategy, and transient response - with hands-on bench experience using precision shunts, isolated differential probes, and VNA-based PDN impedance measurement

- Expertise with multi-phase solutions with high dynamic content and low tolerance.

- Experience with VR tuning to a well defined power test plan to ensure VR specifications meet CPU/ ASIC

- Demonstrated ability to design experiments that isolate root cause in a complex hardware-software stack, strong oscilloscope and lab instrument fluency (triggering on rare transient events, correlating multi-channel captures), and a track record of finding bugs that only surface under specific workload or environmental conditions

- Relevant experience with Silicon bring ups

Strong candidates may also have experience with (Nice-to-have qualifications)

- Masters Degree in Power Electronics

- Experience with high voltage testing (800V and higher)

- Prior power validation work on AI accelerators, GPUs, or high-performance server platforms, including HBM power characterization or memory power management interfaces

- Experience with OpenBMC, IPMI, or custom BMC firmware for sensor monitoring and power capping; familiarity with LLM infer