Silicon Product and Test Engineer

About the role

You will drive the post-silicon productization of bitcoin mining ASICs from silicon bring-up through high-volume manufacturing. This role owns the end-to-end characterization, yield optimization, and test strategy that ensures silicon meets system-level requirements. You will develop and debug ATE test programs while defining screening methodologies that improve power, performance, and DPPM. The position requires deep collaboration across ASIC Design, ATE, Bench, Systems, Reliability, Foundry, and OSAT partners. You will own data analysis across multiple platforms to drive correlation and system-level performance improvements. This role demands hands-on operation in ambiguous, fast-moving environments with a focus on building and scaling complex hardware products. You will define and support the full stack from wafer-level data to manufacturing KPIs.

Key facts

What you'll do

• Drive post-silicon bring-up, characterization, qualification, and productization activities from first silicon through mass production.
• Develop and optimize wafer sort (CP) and final test (FT) screening strategies to improve power, performance, yield, and DPPM.
• Develop, debug, and maintain ATE test programs and screening methodologies for advanced-node ASICs.
• Define and execute characterization plans across process, voltage, and temperature (PVT) conditions.
• Perform silicon data analysis across CP, FT, Bench, and System platforms to improve correlation and optimize system-level performance.
• Drive DOE planning, execution, and analysis for silicon characterization, yield optimization, and process tuning.
• Collaborate with system and hardware engineers to develop effective ASIC binning methodologies and system optimization strategies.
• Define and support ATE hardware requirements including probe cards, sockets, and load boards.
• Analyze wafer-level and package-level parametric and functional data to identify trends, root-cause failures, and drive corrective actions.
• Engage with foundry, OSAT, and external vendors to support bring-up, qualification, yield improvement, and manufacturing execution.
• Develop KPIs and dashboards to track power, performance, process variation, yield, and product quality metrics.
• Execute risk mitigation and contingency plans for yield ramps based on real-time data signals and correlation insights.
• Partner with firmware and systems teams to align test criteria with bootflow, functional coverage, and field behavior.
• Champion continuous improvement initiatives to refine test coverage, reduce test time, and increase throughput.

Requirements

• Hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Possess 5-10 years of experience in Product Engineering, Test Engineering, Silicon Validation, or Post-Silicon Engineering in fabless or semiconductor environments.
• Demonstrate a strong understanding of semiconductor manufacturing flows including wafer sort (CP), final test (FT), qualification, and high-volume manufacturing.
• Show proven experience with silicon bring-up, characterization, yield analysis, and product qualification for advanced-node ASICs or SoCs.
• Have hands-on experience with ATE platforms such as Advantest 93K or Chroma.
• Bring experience developing or debugging ATE test programs and production screening methodologies.
• Exhibit strong statistical data analysis and debugging skills using tools such as JMP, Python, or similar analysis frameworks.
• Have experience with DOE planning, silicon correlation, and yield optimization methodologies.
• Demonstrate a history of collaborating cross-functionally across Design, Systems, Firmware, Reliability, Manufacturing, Foundry, and OSAT teams.
• Show strong problem-solving skills with the ability to independently drive technical issues to closure.
• Comfortably operate in ambiguous, fast-moving environments with a high degree of ownership.
• Adhere to strict quality standards and compliance requirements inherent in semiconductor manufacturing and customer specifications.
• Communicate technical findings clearly and concisely to both technical and cross-functional stakeholders.
• Maintain up-to-date knowledge of test methodologies, process control plans, and industry best practices for advanced-node ASICs.

Nice to have

• Experience with near-threshold operation or low-voltage optimization.
• Experience with high-performance computing, AI, networking, or bitcoin mining ASICs.

Practical notes

The role is based in Toronto, Ontario, Canada. Engagement terms are specified in the source details and must be reviewed for full clarity. No additional benefits or compensation details are provided in the source.